I think it was written by Pawel Worach.

llvm-svn: 128268

delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 instructions, and add a test case for that.

llvm-svn: 128249

the change to ("tLDMIA", "tLDMIA_UPD").  Update the conflict resolution code and add
test cases for that.

llvm-svn: 128247

According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available.
Ignore tSTMIA for the decoder emitter and add a test case for that.

llvm-svn: 128246

llvm-svn: 128236

Set the encoding bits to {0,?,?,0}, not 0.  Plus delegate the disassembly of ADR to
the more generic ADDri/SUBri instructions, and add a test case for that.

llvm-svn: 128234

kind, and fix serialization/deserialization of IdentifierInfo
attributes. These are requires for the new 'availability' attribute.

llvm-svn: 128130

llvm-svn: 128020

code below it. Even though it looks very similar, it will match more precisely
and geneate better functions in the long run.

llvm-svn: 127991

This is a helper class that will make it easier to say which InstAliases can be
printed and which cannot (because of ambiguity).

llvm-svn: 127990

* Move the code that emits the reg in reg class matching into its own function.

llvm-svn: 127988

llvm-svn: 127888

On MSVCRT and compatible, output of %e is incompatible to Posix by default. Number of exponent digits should be at least 2. "%+03d"

FIXME: Implement our formatter in future!
llvm-svn: 127872

On Win32 console, emitting char to col#79 causes linefeed, and the cursor will not return to col#79 upper line with backspace.

llvm-svn: 127696

nothing more than a bitcast.
- Teach tablegen to automatically infer "Bitcast" property.

llvm-svn: 127667

instruction set.  This code adds support for the VEX prefix
and for the YMM registers accessible on AVX-enabled
architectures.  Instruction table support that enables AVX
instructions for the disassembler is in an upcoming patch.

llvm-svn: 127644

llvm-svn: 127619

llvm-svn: 127592

llvm-svn: 127575

llvm-svn: 127517

llvm-svn: 127510

llvm-svn: 127509

llvm-svn: 127508

llvm-svn: 127506

llvm-svn: 127491

as for VDUP32d and VDUP32q, respectively.

llvm-svn: 127489

llvm-svn: 127488

and VDUPLN32d, respectively.

llvm-svn: 127486

as for VREV64d32 and VREV64q32, respectively.

llvm-svn: 127485

the diagnostic.

llvm-svn: 127480

CodeGenRegister entries. Use this information to more intelligently build
the literal register entires in the DAGISel matcher table. Specifically,
use a single-byte OPC_EmitRegister entry for registers with a value of
less than 256 and OPC_EmitRegister2 entry for registers with a larger value.

rdar://9066491

llvm-svn: 127456

llvm-svn: 127448

llvm-svn: 127447

llvm-svn: 127446

llvm-svn: 127445

llvm-svn: 127434

llvm-svn: 127419

llvm-svn: 127262

llvm-svn: 127240

llvm-svn: 127224