to be really bad. Once they are joined they are not broken apart. Also, physical
intervals cannot be spilled!

Added a heuristic as a workaround for this. Be careful coalescing with a
physical register if the virtual register uses are "far". Check if there are
uses in the same loop as the source (copy instruction). Check if it is in the
loop preheader, etc.

llvm-svn: 35134

llvm-svn: 35133

in that BB.

llvm-svn: 35132

llvm-svn: 35127

llvm-svn: 35126

computation used as GEP indexes and if the expression can be folded into
target addressing mode of GEP load / store use types.

llvm-svn: 35123

folded into target addressing mode for the given type.

llvm-svn: 35121

llvm-svn: 35117

it as a late BURR scheduling tie-breaker.
Intuitively, it's good to push down instructions whose results are liveout so
their long live ranges won't conflict with other values which are needed inside
the BB. Further prioritize liveout instructions by the number of operands which
are calculated within the BB.

llvm-svn: 35109

e.g.
t1 = op t2, c1
t3 = op t4, c2
and the following instructions are both ready.
t2 = op c3
t4 = op c4

Then schedule t2 = op first.
i.e.
t4 = op c4
t2 = op c3
t1 = op t2, c1
t3 = op t4, c2

This creates more short live intervals which work better with the register
allocator.

llvm-svn: 35089

More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale.

llvm-svn: 35076

alive in one of the successor block. Do not add it to the kill list.

llvm-svn: 35041

llvm-svn: 35040

llvm-svn: 35039

llvm-svn: 35033

llvm-svn: 35025

zext/sext/aext stuff.

llvm-svn: 35008

llvm-svn: 35007

llvm-svn: 35005

Mingw32/Cygwin targets. This fixes PR978

llvm-svn: 35000

llvm-svn: 34985

llvm-svn: 34984

the lo-reg first.  This is fallout from my ppc calling conv change yesterday,
it fixes test/ExecutionEngine/2003-05-06-LivenessClobber.llx

llvm-svn: 34983

llvm-svn: 34981

llvm-svn: 34965

Register scavenger is now capable of scavenging. It spills a register whose use of furthest away to make it available.

llvm-svn: 34964

enumeration.

llvm-svn: 34960

llvm-svn: 34917

llvm-svn: 34913

llvm-svn: 34910

addc, turn it into add.

This allows us to compile:

long long test(long long A, unsigned B) {
  return (A + ((long long)B << 32)) & 123;
}

into:

_test:
        movl $123, %eax
        andl 4(%esp), %eax
        xorl %edx, %edx
        ret

instead of:
_test:
        xorl %edx, %edx
        movl %edx, %eax
        addl 4(%esp), %eax   ;; add of zero
        andl $123, %eax
        ret

llvm-svn: 34909

llvm-svn: 34908

llvm-svn: 34903

llvm-svn: 34893

This "fixes" PR1238.

llvm-svn: 34890

llvm-svn: 34878

llvm-svn: 34875

entry (0x8b056f0, LLVM BB @0x8b01b30, ID#0):
Live Ins: %r0 %r1 %r2 %r3
        %reg1032 = tMOVrr %r3<kill>
        %reg1033 = tMOVri8 1
        %reg1034 = tMOVri8 0
        tCMPi8 %reg1029<kill>, 0
        tBcc mbb<entry,0x8b06a10>, 0
    Successors according to CFG: 0x8b06980 0x8b06a10

entry (0x8b06980, LLVM BB @0x8b01b30, ID#12):
    Predecessors according to CFG: 0x8b056f0
        %reg1036 = tMOVrr %reg1034<kill>
    Successors according to CFG: 0x8b06a10

entry (0x8b06a10, LLVM BB @0x8b01b30, ID#13):
    Predecessors according to CFG: 0x8b056f0 0x8b06980
        %reg1024<dead> = tMOVrr %reg1030<kill>
        ...

reg1030 and r1 have already been joined. When reg1024 and reg1030 are joined,
r1 live range from function entry to the tMOVrr instruction are dead. Eliminate
r1 from the livein set of the entry BB, not the BB where the copy is.

llvm-svn: 34866

llvm-svn: 34844

llvm-svn: 34843