Original patch by Chris Wailes

llvm-svn: 194143

Presence of using namespace llvm depended on several #ifdef's, and
this broke the build on mswin32.

llvm-svn: 194142

Also, properly name the functions.

llvm-svn: 194141

Original patch by Chris Wailes

llvm-svn: 194140

Original patch by Chris Wailes

llvm-svn: 194139

llvm-svn: 194138

Original patch by Chris Wailes

llvm-svn: 194137

llvm-svn: 194136

Original patch by Chris Wailes

llvm-svn: 194135

llvm-svn: 194126

llvm-svn: 194123

llvm-svn: 194118

Patch by Michele Scandale!

Rewrite of the functions used to compute the backedge taken count of a
loop on LT and GT comparisons.

I decided to split the handling of LT and GT cases becasue the trick
"a > b == -a < -b" in some cases prevents the trip count computation
due to the multiplication by -1 on the two operands of the
comparison. This issue comes from the conservative computation of
value range of SCEVs: taking the negative SCEV of an expression that
have a small positive range (e.g. [0,31]), we would have a SCEV with a
fullset as value range.

Indeed, in the new rewritten function I tried to better handle the
maximum backedge taken count computation when MAX/MIN expression are
used to handle the cases where no entry guard is found.

Some test have been modified in order to check the new value correctly
(I manually check them and reasoning on possible overflow the new
values seem correct).

I finally added a new test case related to the multiplication by -1
issue on GT comparisons.

llvm-svn: 194116

One of the uses of the IsValid flag is to support default constructing
a ErrorOr that is not a Error or a Value. There is not much value in
doing that IMHO. If ErrorOr was to have a default constructor, it
should be implemented by default constructing the value, but even that
looks unnecessary.

The other use is to avoid calling destructors on moved objects. This
looks wrong. If the data being moved has non trivial treatment of
moves (an std::vector for example), it is its destructor that should
handle it, not ~ErrorOr.

With this change ErrorOr becomes a fairly simple wrapper and should
always be better than using an error_code + value in an API.

llvm-svn: 194109

from MipsConstantIslands. 

llvm-svn: 194108

MorphNodeTo is not safe to call during DAG building. It eagerly
deletes dependent DAG nodes which invalidates the NodeMap. We could
expose a safe interface for morphing nodes, but I don't think it's
worth it. Just create a new MachineNode and replaceAllUsesWith.

My understaning of the SD design has been that we want to support
early target opcode selection. That isn't very well supported, but
generally works. It seems reasonable to rely on this feature even if
it isn't widely used.

llvm-svn: 194102

we don't have such an operand.
Suprisingly enough, this is never actually accounted for in the 
ARM version when determining offset ranges. In both places there is the
comment:
-    // FIXME: Make use full range of soimm values.
(soimm = shift operand immediate).

llvm-svn: 194101

alignment will be handled differently than in ARM constant islands.

llvm-svn: 194096

Cortex-M0 supports these 32-bit instructions despite being Thumb1 only
(mostly). We knew about that but not that the aliases without the default "sy"
operand were also permitted.

llvm-svn: 194094

Patch by MathOnNapkins

llvm-svn: 194093

They just propagate out the bitcode reader error, so we don't need a new enum.

llvm-svn: 194091

llvm-svn: 194085

llvm-svn: 194084

[objc-arc] Convert the one directional retain/release relation assert to a conditional check + fail.

Due to the previously added overflow checks, we can have a retain/release
relation that is one directional. This occurs specifically when we run into an
additive overflow causing us to drop state in only one direction. If that
occurs, we should bail and not optimize that retain/release instead of
asserting.

Apologies for the size of the testcase. It is necessary to cause the additive
cfg overflow to trigger.

rdar://15377890

llvm-svn: 194083

This was only working previously due to a quirk in the way lit
concatenates script commands.

llvm-svn: 194078

llvm-svn: 194077

Original patch by David Monniaux

llvm-svn: 194075

Original patch by David Monniaux

llvm-svn: 194074

Original patch by Damien Schoof

llvm-svn: 194067

command regarding the porting from the ARM version (was an old comment).

llvm-svn: 194066

llvm-svn: 194065

Original patch by Jonathan Ragan-Kelley

llvm-svn: 194064

llvm-svn: 194062

All other tools have this -- it's needed to avoid hanging lit on Windows in
case of a crash.

llvm-svn: 194060

All other custom operations tags have LLVM prefix.

llvm-svn: 194058

Workaround for an OCaml bug:
http://caml.inria.fr/mantis/view.php?id=4166

llvm-svn: 194057

Submit the basic port of the rest of ARM constant islands code to Mips. 
Two test cases are added which reflect the next level of functionality:
constants getting moved to water areas that are out of range from the
initial placement at the end of the function and basic blocks being split to
create water when none exists that can be used. There is a bunch of this
code that is not complete and has been marked with IN_PROGRESS. I will
finish cleaning this all up during the next week or two and submit the
rest of the test cases. I have elminated some code for dealing with
inline assembly because to me it unecessarily complicates things and
some of the newer features of llvm like function attributies and builtin
assembler give me better tools to solve the alignment issues created
there. Also, for Mips16 I even have the option of not doing constant
islands in the present of inline assembler if I chose. When everything
has been completed I will summarize the port and notify people that
are knowledgable regarding the ARM Constant Islands code so they can
review it in it's entirety if they wish.

llvm-svn: 194053

These were incorrectly pointing to HAVE_LOG despite being checked for
correctly in config-ix.cmake.

Patch by James Lyon!

llvm-svn: 194051

llvm-svn: 194048

Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post).
Including following 14 instructions:
4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4).

llvm-svn: 194043