some of the latency computation logic out of the SDNode
ScheduleDAG code into a TargetInstrItineraries helper method
to help with this.

llvm-svn: 59761

condition in an addition operation.

llvm-svn: 59760

the RR scheduler actually does look at latency values, but it
doesn't use a hazard recognizer so it has no way to know when
a no-op is needed, as opposed to just stalling and incrementing
the cycle count.

llvm-svn: 59759

llvm-svn: 59758

inlining function, then increase the stack protection level on the inlining
function.

llvm-svn: 59757

that an overflow/carry occured. These are converted into ISD::[SU]ADDO nodes,
which are lowered in a target-independent way into something sane. Eventually,
each target can implement their own method of checking the overflow/carry flags.

llvm-svn: 59756

llvm-svn: 59755

llvm-svn: 59754

llvm-svn: 59753

llvm-svn: 59752

MachineInstr scheduling DAG, meaning they implicitly depend on all
preceding defs. This fixes Benchmarks/Shootout-C++/except and
Regression/C++/EH/simple_rethrow in
  -relocation-model=pic -disable-post-RA-scheduler=false
mode.

llvm-svn: 59747

llvm-svn: 59746

llvm-svn: 59745

llvm-svn: 59741

llvm-svn: 59739

(a) Remove moved file (SPUAsmPrinter.cpp) to make svn happy.
(b) Remove truncated stores that will never be used.
(c) Add initial support for __muldi3 as a libcall.

llvm-svn: 59734

llvm-svn: 59727

llvm-svn: 59720

llvm-svn: 59718

llvm-svn: 59717

llvm-svn: 59715

promote), fix signed conversion of indexed offsets.

llvm-svn: 59707

llvm-svn: 59705

llvm-svn: 59704

llvm-svn: 59703

llvm-svn: 59702

list-tdrr schedulers into a common base class.

llvm-svn: 59701

dedicated "fast" scheduler in -fast mode instead, which is
faster. This speeds up llc -fast by a few percent on some
testcases -- the speedup only happens for code not handled by
fast-isel.

llvm-svn: 59700

partially linked objects.

llvm-svn: 59699

the list-burr scheduler so that it can be used by the list-tdrr
scheduler too.

llvm-svn: 59698

- Register scavenger should use MachineRegisterInfo and internal map to find the first use of a register after a given machine instruction.
- When scavenging a register, in addition to the spill, insert a restore before the first use.
- Abort if client is looking to scavenge a register even when a previously scavenged register is still live.

llvm-svn: 59697

llvm-svn: 59696

llvm-svn: 59692

extend it a bit, and make use of it in all schedulers, to
ensure consistent checking.

llvm-svn: 59689

llvm-svn: 59688

llvm-svn: 59681

and CreateClone don't add any extra value.

llvm-svn: 59679

llvm-svn: 59678

llvm-svn: 59677

is currently off by default, and can be enabled with
-disable-post-RA-scheduler=false.

This doesn't have a significant impact on most code yet because it doesn't
yet do anything to address anti-dependencies and it doesn't attempt to
disambiguate memory references. Also, several popular targets
don't have pipeline descriptions yet.

The majority of the changes here are splitting the SelectionDAG-specific
code out of ScheduleDAG, so that ScheduleDAG can be moved to
libLLVMCodeGen.a. The interface between ScheduleDAG-using code and
the rest of the scheduling code is somewhat rough and will evolve.

llvm-svn: 59676