llvm-svn: 138360

llvm-svn: 138354

llvm-svn: 138348

llvm-svn: 138345

llvm-svn: 138344

Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.

llvm-svn: 138341

llvm-svn: 138339

There is no non-writeback store multiple instruction in Thumb1, so
don't define one. As a result load multiple is the only instantiation of
the multiclass, so refactor that away entirely.

llvm-svn: 138338

Fix two more instances of mis-matched operand names breaking disassembly.  Found by randomized testing.

llvm-svn: 138337

Add support for breaking 256-bit v16i16 and v32i8 VSETCC into two 128-bit ones, avoiding sclarization. Add vex form of pcmpeqq and pcmpgtq. Fixes more cases for PR10712.

llvm-svn: 138321

SSE transition penalty. The pass is enabled through the "x86-use-vzeroupper"
llc command line option. This is only the first step (very naive and
conservative one) to sketch out the idea, but proper DFA is coming next
to allow smarter decisions. Comments and ideas now and in further commits
will be very appreciated.

llvm-svn: 138317

llvm-svn: 138311

llvm-svn: 138308

llvm-svn: 138306

llvm-svn: 138301

llvm-svn: 138300

llvm-svn: 138299

llvm-svn: 138298

llvm-svn: 138295

llvm-svn: 138294

llvm-svn: 138292

llvm-svn: 138287

llvm-svn: 138285

It's not playing nicely in the coalescer with the tied operand. Disable
commutability for now while we figure out the deeper fix.

llvm-svn: 138278

Provide operand encoding information for half-precision VCVT instructions.  Found by randomized testing.

llvm-svn: 138273

avoding scalarization of the compare. Reduces code from 59 to 6
instructions. Fix PR10712.

llvm-svn: 138271

llvm-svn: 138270

Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing.

llvm-svn: 138269

llvm-svn: 138258

llvm-svn: 138255

llvm-svn: 138251

llvm-svn: 138249

llvm-svn: 138246

llvm-svn: 138186

llvm-svn: 138177

llvm-svn: 138174

This pleases the register scavenger and brings
test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll a little closer to
working with -verify-machineinstrs.

llvm-svn: 138164

Therefore, rather then generate a pseudo instruction, which is later expanded,
generate the necessary instructions in place.

llvm-svn: 138163

The irony is not lost that this is not a completely trivial patchset.

llvm-svn: 138143

needed for Mips32.

llvm-svn: 138132