llvm-svn: 105492

Copy location info for current function argument from dbg.declare if respective store instruction does not have any location info.

llvm-svn: 105490

llvm-svn: 105488

llvm-svn: 105485

llvm-svn: 105481

llvm-svn: 105480

register allocation.

Process all of the clobber lists at the end of the function, marking the
registers as used in MachineRegisterInfo.

This is necessary in case the calls clobber callee-saved registers (sic).

llvm-svn: 105473

8060143, although this doesn't fix the real problem with tail call.

llvm-svn: 105472

llvm-svn: 105470

llvm-svn: 105461

llvm-svn: 105456

llvm-svn: 105454

replace an OpA with a widened OpB, it is possible to get new uses of OpA due to CSE
when recursively updating nodes.  Since OpA has been processed, the new uses are
not examined again.  The patch checks if this occurred and it it did, updates the
new uses of OpA to use OpB.

llvm-svn: 105453

llvm-svn: 105450

functions where they belong.

llvm-svn: 105449

Add skeleton of support for emitting the list of prototypes for BuiltinsARM.def

llvm-svn: 105443

llvm-svn: 105442

llvm-svn: 105441

llvm-svn: 105440

VECTOR_SHUFFLEs to REG_SEQUENCE instructions.  The standard ISD::BUILD_VECTOR
node corresponds closely to REG_SEQUENCE but I couldn't use it here because
its operands do not get legalized.  That is pretty awful, but I guess it
makes sense for other targets.  Instead, I have added an ARM-specific version
of BUILD_VECTOR that will have its operands properly legalized.
This fixes the rest of Radar 7872877.

llvm-svn: 105439

llvm-svn: 105438

Check that all the instructions are in the same basic block, that the
EXTRACT_SUBREGs write to the same subregs that are being extracted, and that
the source and destination registers are in the same regclass.  Some of
these constraints can be relaxed with a bit more work.  Jakob suggested
that the loop that checks for subregs when NewSubIdx != 0 should use the
"nodbg" iterator, so I made that change here, too.

llvm-svn: 105437

llvm-svn: 105435

llvm-svn: 105427

call version will follow.

llvm-svn: 105422

version will follow.

llvm-svn: 105419

llvm-svn: 105416

llvm-svn: 105414

A temporary flag -arm-tail-calls defaults to off,
so there is no functional change by default.
Intrepid users may try this; simple cases work
but there are bugs.

llvm-svn: 105413

needs to demand the high bits because it's asserting that they're zero.

llvm-svn: 105406

llvm-svn: 105399

llvm-svn: 105397

llvm-svn: 105396

llvm-svn: 105395

llvm-svn: 105390

needed. The result is that now we are able to drop unnecessary symbol from
shared libraries.

llvm-svn: 105389

registers it defines then interfere with an existing preg live range.

For instance, if we had something like these machine instructions:

BB#0
  ... = imul ... EFLAGS<imp-def,dead>
  test ..., EFLAGS<imp-def>
  jcc BB#2 EFLAGS<imp-use>

BB#1
  ... ; fallthrough to BB#2

BB#2
  ... ; No code that defines EFLAGS
  jcc ... EFLAGS<imp-use>

Machine sink will come along, see that imul implicitly defines EFLAGS, but
because it's "dead", it assumes that it can move imul into BB#2. But when it
does, imul's "dead" imp-def of EFLAGS is raised from the dead (a zombie) and
messes up the condition code for the jump (and pretty much anything else which
relies upon it being correct).

The solution is to know which pregs are live going into a basic block. However,
that information isn't calculated at this point. Nor does the LiveVariables pass
take into account non-allocatable physical registers. In lieu of this, we do a
*very* conservative pass through the basic block to determine if a preg is live
coming out of it.

llvm-svn: 105387

implementation. Force the internal one to unbreak clang selfhost on linux.

llvm-svn: 105386

llvm-svn: 105381

arm_neon.h now makes it through clang and generates appropriate code for those functions which can use
generic vector operators rather than __builtin_neon_*

llvm-svn: 105380