llvm-svn: 134893

  and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
  detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
  MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
  MCSubtargetInfo so MC code emitter can do the right thing.

llvm-svn: 134884

llvm-svn: 134882

llvm-svn: 134858

CPU, and feature string. Parsing some asm directives can change
subtarget state (e.g. .code 16) and it must be reflected in other
modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance
must be shared.

llvm-svn: 134795

llvm-svn: 134764

llvm-svn: 134760

llvm-svn: 134758

llvm-svn: 134755

The normal tBX instruction is predicable, so there's no reason the
pseudos for using it as a return shouldn't be. Gives us some nice code-gen
improvements as can be seen by the test changes. In particular, several
tests now have to disable if-conversion because it works too well and defeats
the test.

llvm-svn: 134746

is to use this for architectures that have a native FMA instruction.

llvm-svn: 134742

llvm-svn: 134739

Found by valgrind.

llvm-svn: 134738

No functional change.

llvm-svn: 134737

llvm-svn: 134734

llvm-svn: 134732

llvm-svn: 134729

Fix a FIXME.

llvm-svn: 134727

llvm-svn: 134721

llvm-svn: 134719

No functional change.

llvm-svn: 134714

TableGen'erated MC lowering pseudo-expansion.

llvm-svn: 134712

llvm-svn: 134707

Hook up the TableGen lowering for simple pseudo instructions for ARM and
use it for a subset of the many pseudos the backend has as proof of concept.

More conversions to come.

llvm-svn: 134705

- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen uses
  to generate asm matcher subtarget feature queries. e.g.
  "ModeThumb,FeatureThumb2" is translated to
  "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".

llvm-svn: 134678

llvm-svn: 134627

llvm-svn: 134626

llvm-svn: 134616

llvm-svn: 134614

multiply-accumulate instructions with separate rounding steps.

llvm-svn: 134609

llvm-svn: 134608

llvm-svn: 134606

Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests.

llvm-svn: 134590

Factor ARM triple parsing out of ARMSubtarget. Another step towards making ARM subtarget info available to MC.

llvm-svn: 134569

llvm-svn: 134547

This allows us to remove the (bogus and unneeded) encoding information from
the pseudo-instruction class definitions. All of the pseudos that haven't
been converted yet and still need encoding information instance from the normal
instruction classes and explicitly set isCodeGenOnly, and so are distinct
from this change.

llvm-svn: 134540

Pseudo-instructions don't have encoding information, as they're lowered
to real instructions by the time we're doing binary encoding.

llvm-svn: 134533

llvm-svn: 134525

If the function allocates reserved stack space for callee argument frames,
estimateStackSize() needs to account for that, as it doesn't show up as
ordinary frame objects. Otherwise, a callee with a large argument list will
throw off the calculations for whether to allocate an emergency spill slot
and we get assert() failures in the register scavenger.

rdar://9715469

llvm-svn: 134415

llvm-svn: 134281