llvm-svn: 152203

to hash_combine. One of the interfaces could already do this, and the
other can just use a small buffer. This is a much more efficient way to
use the hash_combine interface, although I don't have any particular
benchmark where this code was hot, so I can't measure much of an impact.
It at least doesn't slow anything down.

llvm-svn: 152200

"is sized". This prevents every query to isSized() from recursing over
every sub-type of a struct type. This could get *very* slow for
extremely deep nesting of structs, as in 177.mesa.

This change is a 45% speedup for 'opt -O2' of 177.mesa.linked.bc, and
likely a significant speedup for other cases as well. It even impacts
-O0 cases because so many part of the code try to check whether a type
is sized.

Thanks for the review from Nick Lewycky and Benjamin Kramer on IRC.

llvm-svn: 152197

until after other inexpensive tests.

llvm-svn: 152195

llvm-svn: 152188

llvm-svn: 152185

llvm-svn: 152184

GV and XDOT paths are untested but should work the same.

llvm-svn: 152179

llvm-svn: 152178

Soon, ScheduleDAG will not refer to the BB.

llvm-svn: 152177

llvm-svn: 152176

llvm-svn: 152175

llvm-svn: 152174

llvm-svn: 152173

llvm-svn: 152172

as well as completely defined classes.

This fixes rdar://10956070

llvm-svn: 152171

Extend r148086 to check for [r +/- reg] address mode. This fixes queens performance regression (due to increased register pressure from overly aggressive pre-inc formation).

llvm-svn: 152162

Register pair, all lanes subscripting.

llvm-svn: 152157

llvm-svn: 152153

Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.

llvm-svn: 152150

SmallPtrSet: Provide a more efficient implementation of swap than the default triple-copy std::swap.

This currently assumes that both sets have the same SmallSize to keep the implementation simple,
a limitation that can be lifted if someone cares.

llvm-svn: 152143

llvm-svn: 152136

llvm-svn: 152131

llvm-svn: 152129

llvm-svn: 152127

llvm-svn: 152122

implementation. Patch by Meador Inge

llvm-svn: 152116

When an instruction only writes sub-registers, it is still necessary to
add an <imp-def> operand for the super-register.  When reloading into a
virtual register, rewriting will add the operand, but when loading
directly into a virtual register, the <imp-def> operand is still
necessary.

llvm-svn: 152095

llvm-svn: 152089

Make it possible for a target to mark FSUB as Expand.  This requires providing a default expansion (FADD+FNEG), and teaching DAGCombine not to form FSUBs post-legalize if they are not legal.

llvm-svn: 152079

The fpscr register contains both flags (set by FP operations/comparisons) and
control bits. The control bits (FPSCR) should be reserved, since they're always
available and needn't be defined before use. The flag bits (FPSCR_NZCV) should
like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165.

llvm-svn: 152076

llvm-svn: 152070

rdar://10988114

llvm-svn: 152068

llvm-svn: 152066

Use the new composite physical registers.

llvm-svn: 152063

llvm-svn: 152061

With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.

llvm-svn: 152045

Used to allow context sensitive printing of super-register or sub-register
references.

llvm-svn: 152043

Patch by Sean Silva!

llvm-svn: 152042

Specifically, remove the magic number when checking to see if the copy has a 
glue operand and simplify the checking logic.

rdar://10930395

llvm-svn: 152041