methods, infer their self's type as their result type.
// rdar://15145218

llvm-svn: 192377

llvm-svn: 192376

llvm-svn: 192375

This fixes getSystemRegistryString() in WindowsToolChain.cpp to
make sure that the VS version that it picks has an InstallDir.
Previously we would look for the highest version os VS and check
for InstallDir afterwards.

Patch by Yaron Keren!

llvm-svn: 192374

Fixed an issue where environment variables that contained special characters '$' and '#' would hose up the GDB server packet. We now use the QEnvironmentHexEncoded packet that has existed for a long time when we need to. Also added code that will stop sending the QEnvironmentHexEncoded and QEnvironment packets if they aren't supported.

llvm-svn: 192373

Removed the -t options from linking flags to avoid having the linker print out all .o files it was linking with.

llvm-svn: 192372

Patch by Josh Samuel!

llvm-svn: 192371

We previously failed to check whether the SUCCESS variable was set,
and would thus always exit with a failure if vs2012 didn't exist.

llvm-svn: 192370

llvm-svn: 192369

This is only a step to clean the buildbot.

llvm-svn: 192368

The function is used by the machine verifier and checks that VOP*
instructions have legal operands.

llvm-svn: 192367

We can't enable the verifier for tests with SI_IF and SI_ELSE, because
these instructions are always followed by a COPY which copies their
result to the next basic block.  This violates the machine verifier's
rule that non-terminators can not folow terminators.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 192366

During instruction selection, we rewrite the destination register
class for MIMG instructions based on their writemasks.  This creates
machine verifier errors since the new register class does not match
the register class in the MIMG instruction definition.

We can avoid this by defining different MIMG instructions for each
possible destination type and then switching to the correct instruction
when we change the register class.

llvm-svn: 192365

This prevents the machine verifier from complaining about uses of
an undefined physical register.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 192364

StructurizeCFG pass allows to make complex cfg reducible ; it allows a lot of
shader from shadertoy (which exhibits complex control flow constructs) to works
correctly with respect to CFG handling (and allow us to detect potential bug in
other part of the backend).

We provide a cmd line argument to disable the pass for debug purpose.

Patch by: Vincent Lejeune

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 192363

Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).

llvm-svn: 192362

Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).

llvm-svn: 192361

llvm-svn: 192360

llvm-svn: 192359

On at least FreeBSD and NetBSD there is an extra field in the dyld link
map struct.  I've left an assert for other OSes (i.e., Linux/mips) until
it's determined if they do the same.

llvm-svn: 192358

Replace duplicate code snippet with function.

llvm-svn: 192357

This reverts commit r192351. The LLVM side broke the build and the Clang tests
will inevitably fail without it.

llvm-svn: 192356

The annotations are AnnotateIgnoreSyncBegin/End,
may be useful to ignore some infrastructure synchronization
that introduces lots of false negatives.

llvm-svn: 192355

Revert "Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4)."

This reverts commit r192352. It broke the build.

llvm-svn: 192354

This reverts commit r192300.

The change itself looks correct, but it found issues on how we handle aliases
in llvm.

llvm-svn: 192353

Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).

llvm-svn: 192352

Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).

E.g. ld1(3 registers version) will load 32-bit elements {A, B, C, D, E, F} sequentially into the three 64-bit vectors list {BA, DC, FE}.
E.g. ld3 will load 32-bit elements {A, B, C, D, E, F} into the three 64-bit vectors list {DA, EB, FC}.

llvm-svn: 192351

llvm-svn: 192350

Summary: Colon was incorrectly detected as a start of inheritance list. Fixed.

Reviewers: djasper

Reviewed By: djasper

CC: cfe-commits, klimek

Differential Revision: http://llvm-reviews.chandlerc.com/D1884

llvm-svn: 192349

llvm-svn: 192348

Use the existing convenience function.

llvm-svn: 192347

Emit a proper error instead of crashing in CodeGen. PR16892.

llvm-svn: 192345

When we had a sequence like:

    s1 = VLDRS [r0, 1], Q0<imp-def>
    s3 = VLDRS [r0, 2], Q0<imp-use,kill>, Q0<imp-def>
    s0 = VLDRS [r0, 0], Q0<imp-use,kill>, Q0<imp-def>
    s2 = VLDRS [r0, 4], Q0<imp-use,kill>, Q0<imp-def>

we were gathering the {s0, s1} loads below the s3 load. This is fine,
but confused the verifier since now the s3 load had Q0<imp-use> with
no definition above it.

This should mark such uses <undef> as well. The liveness structure at
the beginning and end of the block is unaffected, and the true sN
definitions should prevent any dodgy reorderings being introduced
elsewhere.

rdar://problem/15124449

llvm-svn: 192344

The patch reviewed by Rafael Espindola.
http://llvm-reviews.chandlerc.com/D1843

llvm-svn: 192343

-- so that command line options to specify new input files, such as
/defaultlib:foo, is handled properly. Such options were ignored before
this patch.

llvm-svn: 192342

llvm-svn: 192341

llvm-svn: 192340

llvm-svn: 192339

llvm-svn: 192338

Differential Revision: http://llvm-reviews.chandlerc.com/D1881

llvm-svn: 192337