llvm-svn: 104580

llvm-svn: 104573

llvm-svn: 104571

version of t2MVN already allowed that, but not the register versions.

llvm-svn: 104570

llvm-svn: 104564

structure that represents a mapping without any dependencies on SubRegIndex
numbering.

This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.

llvm-svn: 104563

llvm-svn: 104544

Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.

llvm-svn: 104531

llvm-svn: 104518

Add assertions in places that depend on consecutive indices.

llvm-svn: 104510

from ARMRegisterInfo.h

llvm-svn: 104508

llvm-svn: 104455

llvm-svn: 104421

Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.

llvm-svn: 104419

copying VFP subregs.  This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.

llvm-svn: 104415

Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).

llvm-svn: 104307

Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.

llvm-svn: 104293

This fixes the remaining issue with pr7167.

llvm-svn: 104257

Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace.

llvm-svn: 104147

t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.

llvm-svn: 104115

llvm-svn: 104114

Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.

llvm-svn: 104111

llvm-svn: 104110

Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.

llvm-svn: 104102

Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649

llvm-svn: 104060

too large limit.

The function would return immediately when finding an addrmode 3/5 instruction.
It needs to keep scanning in case there is an addrmode 6 instruction which drops
the limit to 0.

A test case is very difficult to produce because it will only fail when the
scavenger is used.

rdar://problem/7894847

llvm-svn: 103995

llvm-svn: 103982

Obvious in retrospect but not fun to debug.

llvm-svn: 103969

Using NEON load / store multiple instructions will no longer create gobs of vmov of D registers!

llvm-svn: 103960

llvm-svn: 103917

llvm-svn: 103903

llvm-svn: 103901

llvm-svn: 103898

This can be extended later on to handle more "complex" constants.

llvm-svn: 103881

Temporary emit it as raw bytes until it will be added to binutils as well.

llvm-svn: 103878

llvm-svn: 103868

llvm-svn: 103855

allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.

llvm-svn: 103854

llvm-svn: 103851

instructions.

e.g.
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1027<def> = EXTRACT_SUBREG %reg1026, 6
%reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5
...
%reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12

After REG_SEQUENCE is eliminated, we are left with:

%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
%reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5

The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't
know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the
target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger
sub-register (or combined to be reg1026 itself as is the case here). If it is possible, 
it will be able to replace references of reg1026 with reg1029 + the larger sub-register
index.

llvm-svn: 103835