LiveIntervals::findLiveInMBBs has to do a full binary search for each segment.

llvm-svn: 129292

llvm-svn: 129288

llvm-svn: 129287

invalid instructions.

llvm-svn: 129286

disassembler API.  Hooked this up to the ARM target so such tools as Darwin's
otool(1) can now print things like branch targets for example this:
  blx _puts
instead of this:
  blx #-36
And even print the expression encoded in the Mach-O relocation entried for
things like this:
  movt r0, :upper16:((_foo-_bar)+1234)

llvm-svn: 129284

Both coalescing and register allocation already check aliases for interference,
so these extra segments are only slowing us down.

This speeds up both linear scan and the greedy register allocator.

llvm-svn: 129283

This particularly helps with the initial transfer of fixed intervals.

llvm-svn: 129277

llvm-svn: 129276

In particular, don't repeatedly recompute the PIC base live range after rematerialization.

llvm-svn: 129275

was always a User.

llvm-svn: 129272

llvm-svn: 129271

an odd number.

llvm-svn: 129270

--- Reverse-merging r129235 into '.':
D    test/Feature/bb_attrs.ll
U    include/llvm/BasicBlock.h
U    include/llvm/Bitcode/LLVMBitCodes.h
U    lib/VMCore/AsmWriter.cpp
U    lib/VMCore/BasicBlock.cpp
U    lib/AsmParser/LLParser.cpp
U    lib/AsmParser/LLLexer.cpp
U    lib/AsmParser/LLToken.h
U    lib/Bitcode/Reader/BitcodeReader.cpp
U    lib/Bitcode/Writer/BitcodeWriter.cpp

llvm-svn: 129259

llvm-svn: 129248

* Add a "landing pad" attribute to the BasicBlock.
* Modify the bitcode reader and writer to handle said attribute.

Later: The verifier will ensure that the landing pad attribute is used in the
appropriate manner. I.e., not applied to the entry block, and applied only to
basic blocks that are branched to via a `dispatch' instruction.

(This is a work-in-progress.)

llvm-svn: 129235

InstAlias doesn't allow matching immediate operands, so we have to write
C++ code to do this.

llvm-svn: 129223

llvm-svn: 129214

And don't append the name over and over again in the loop.

llvm-svn: 129210

llvm-svn: 129209

is an array of structures doesn't imply it's a ConstantArray of
ConstantStruct.

llvm-svn: 129207

llvm-svn: 129203

delete the instruction pointed to by CGP's current instruction
iterator, leading to a crash on the testcase.  This fixes PR9578.

llvm-svn: 129200

Switch lowering probably shouldn't be using FP for this.  This resolves PR9581.

llvm-svn: 129199

it's completely safe to cache the AST across LICM runs even with this fix,
but this fix can't hurt.

llvm-svn: 129198

llvm-svn: 129193

It is common for large live ranges to have few basic blocks with register uses
and many live-through blocks without any uses. This approach grows the Hopfield
network incrementally around the use blocks, completely avoiding checking
interference for some through blocks.

llvm-svn: 129188

This doesn't require seeking in the live interval union, so it is very cheap.

llvm-svn: 129187

with undef arguments.

llvm-svn: 129185

error stream, in cases where the AsmParser is
being invoked by EDDisassembler.  Before, they
were being sent to errs() because no error handler
was installed in the SourceMgr.

llvm-svn: 129177

Simplify array bound checks and clarify comments.  One element array can have same non-zero number as lower bound as well as upper bound.

llvm-svn: 129170

can be used even when main() isn't present in the Module, but it means that you
don't get to read argv[].

llvm-svn: 129163

llvm-svn: 129160

If lower bound is more then upper bound then consider it is an unbounded array.
An array is unbounded if non-zero lower bound is same as upper bound.
If lower bound and upper bound are zero than array has one element.

llvm-svn: 129156

Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap is lowered into a call to the specified trap function at sdisel time.

llvm-svn: 129152

llvm-svn: 129149

llvm-svn: 129148

PR9650
rdar://problem/9257565

llvm-svn: 129147

PR9648
rdar://problem/9257634

llvm-svn: 129146

The previous cleanup of LDRD got overzealous and removed it, causing post-RA
scheduling to get overzealous in breaking antidependencies and invalidate these instructions. Hilarity and invalid assembly ensued.

rdar://9244161

llvm-svn: 129144

Teach 32-bit section loading to use the Memory Manager interface, just like
the 64-bit loading does. Tidy up a few other things here and there.

llvm-svn: 129138