Anton for half of this patch.

llvm-svn: 37641

Look for VECTOR_SHUFFLE that's identity operation on either LHS or RHS. This can happen before DAGCombiner catches it.

llvm-svn: 37636

llvm-svn: 37625

define double @test2(i64 %A) {
   %B = bitcast i64 %A to double
   ret double %B
}

$ llvm-as < t.ll | llc -march=x86-64

before:

         .align  4
         .globl  _test2
_test2:
         movd %rdi, %xmm0
         ret

after:

_test2:
         subq $8, %rsp
         movq %rdi, (%rsp)
         movsd (%rsp), %xmm0
         addq $8, %rsp
         ret

llvm-svn: 37617

llvm-svn: 37611

llvm-svn: 37606

llvm-svn: 37579

llvm-svn: 37578

implementation for x86.

llvm-svn: 37576

llvm-svn: 37574

llvm-svn: 37572

llvm-svn: 37571

llvm-svn: 37534

llvm-svn: 37533

llvm-svn: 37528

llvm-svn: 37527

llvm-svn: 37517

llvm-svn: 37516

Stupid cut-n-paste bug caused me soooo much grief. Why wasn't there a compilation warning? I blame it on the FE folks.

llvm-svn: 37484

llvm-svn: 37468

llvm-svn: 37466

- Modifications from the last patch included
  (issues pointed by Evan Cheng are now fixed).
- Added more MipsI instructions.
- Added more patterns to match branch instructions.

llvm-svn: 37461

llvm-svn: 37437

llvm-svn: 37434

llvm-svn: 37419

switches.  There is one really easy isel thing here with tst we are not
getting.

llvm-svn: 37400

llvm-svn: 37388

llvm-svn: 37385

llvm-svn: 37381

smaller than the preferred alignment, but so that the target can actually
specify a minimum alignment if needed.  This fixes some objc protocol
failures Devang tracked down.

llvm-svn: 37373

For VFP2 fldm, fstm instructions, the condition code is printed after the address mode and size specifier. e.g. fstmiaseq, not fstmeqias.

llvm-svn: 37351

llvm-svn: 37349

llvm-svn: 37342

llvm-svn: 37341

llvm-svn: 37340

llvm-svn: 37320

llvm-svn: 37308

llvm-svn: 37307

llvm-svn: 37289

for a target-dependent default with a command-line override; this way
should be generally usable.

llvm-svn: 37285