llvm-svn: 199316

llvm-svn: 199315

llvm-svn: 199033

The implicit immediate 0 forms are assembly aliases, not distinct instruction
encodings.  Fix the initial implementation introduced in r198914 to an alias to
avoid two separate instruction definitions for the same encoding.

An InstAlias is insufficient in this case as the necessary due to the need to
add a new additional operand for the implicit zero.  By using the AsmPsuedoInst,
fall back to the C++ code to transform the instruction to the equivalent
_POST_IMM form, inserting the additional implicit immediate 0.

llvm-svn: 199032

The disassembler would no longer be able to disambiguage between the two
variants (explicit immediate #0 vs implicit, omitted #0) for the ldrt, strt,
ldrbt, strbt mnemonics as both versions indicated the disassembler routine.

llvm-svn: 198944

llvm-svn: 198738

llvm-svn: 198591

Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits.

llvm-svn: 198278

llvm-svn: 198269

llvm-svn: 198268

Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases.

llvm-svn: 198265

llvm-svn: 198013

llvm-svn: 197984

The tests for the disassembler were adapted from the encoder tests, and for the
most part, the output from the disassembler matches that encoder-test inputs.
There are some places where more-informative mnemonics could be produced
(notably for the branch instructions), and those cases are noted in the tests
with FIXMEs.

Future work includes:

 - Generating more-informative mnemonics when possible (this may also be done
   in the printer).

 - Remove the dependence on positional "numbered" operand-to-variable mapping
   (for both encoding and decoding).

 - Internally using 64-bit instruction variants in 64-bit mode (if this turns
   out to matter).

llvm-svn: 197693

llvm-svn: 195936

llvm-svn: 195903

llvm-svn: 195803

instructions.

llvm-svn: 195788

ie. echo "0x00 0x04 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
    echo "0x00 0x00 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
will be disassembled into the same instruction st1 {v0b}[0], [x0], x0.

llvm-svn: 195591

llvm-svn: 195078

llvm-svn: 194648

At the moment this is just the MC support.

llvm-svn: 194585

llvm-svn: 194569

copy in MC layer. Added the MC layer tests.  Fixed triple setting in test cases.

Patch by Ana Pazos <apazos@codeaurora.org>.

llvm-svn: 194501

llvm-svn: 194416

llvm-svn: 194394

[ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (Thumb encodings)

llvm-svn: 194263

llvm-svn: 194262

llvm-svn: 194261

llvm-svn: 194205

llvm-svn: 194123

llvm-svn: 194118

Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post).
Including following 14 instructions:
4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4).

llvm-svn: 194043

llvm-svn: 193992

llvm-svn: 193816

llvm-svn: 193790

This adds a new subtarget feature called FPARMv8 (implied by NEON), and
predicates the support of the FP instructions and registers on this feature.

llvm-svn: 193739

llvm-svn: 193705

llvm-svn: 193691

llvm-svn: 193623