llvm-svn: 105344

and tidy up the comment describing it.

llvm-svn: 105339

llvm-svn: 105335

llvm-svn: 105109

llvm-svn: 105108

llvm-svn: 105107

llvm-svn: 105106

Schedule high latency instructions for latency reduction even if they are not vfp / NEON instructions.

llvm-svn: 105060

llvm-svn: 104980

llvm-svn: 104974

make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n.

llvm-svn: 104967

the instruction class for t2RSB to add that operand in svn r104582.
Radar 8033757.

llvm-svn: 104907

an alloca() or an llvm.stackrestore(). rdar://8031573

llvm-svn: 104900

llvm-svn: 104899

llvm-svn: 104897

llvm-svn: 104891

should fall through to the 'H' case, but instead 'Q' was falling through to 'R'
so that it would do the wrong thing for a big-endian ARM target.

llvm-svn: 104883

to update the jmpbuf in the presence of VLAs.

llvm-svn: 104862

TableGen shortly.

llvm-svn: 104754

ISD::. No functional change.

llvm-svn: 104734

A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104704

llvm-svn: 104670

Fixing http://llvm.org/bugs/show_bug.cgi?id=7225.

llvm-svn: 104667

llvm-svn: 104661

This reverts commit 104654.

llvm-svn: 104660

A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104654

Fixing http://llvm.org/bugs/show_bug.cgi?id=7222.

llvm-svn: 104653

Fixing http://llvm.org/bugs/show_bug.cgi?id=7221.

llvm-svn: 104652

SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.

llvm-svn: 104627

Add missing implementation to the materialization of VFP misc. instructions (vmrs, vmsr and vmov (immediate))

llvm-svn: 104588

llvm-svn: 104587

I don't know of any particular reason why that would be important, but
neither can I see any reason to disallow it.

llvm-svn: 104583

Thumb2 ADD and SUB instructions: allow RSB instructions be changed to set the
condition codes, and allow RSBS instructions to be predicated.

llvm-svn: 104582

llvm-svn: 104580

llvm-svn: 104573

llvm-svn: 104571

version of t2MVN already allowed that, but not the register versions.

llvm-svn: 104570

llvm-svn: 104564

structure that represents a mapping without any dependencies on SubRegIndex
numbering.

This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.

llvm-svn: 104563

llvm-svn: 104544