Commits · 7dd8c0b9917d1d9af56912cd37120939c6584bf5 · Roger Ferrer / llvm-epi-0.8

Oct 13, 2010
- Add encodings for VNMUL[SD]. · 7dd8c0b9
  Bill Wendling authored Oct 12, 2010
```
llvm-svn: 116375
```
  7dd8c0b9
- Add encodings for VDIV and VMUL. · a06aee82
  Bill Wendling authored Oct 12, 2010
```
llvm-svn: 116370
```
  a06aee82
- Move the ARM so_imm encoding into a custom operand encoder and remove the · 12e493ac
  Jim Grosbach authored Oct 12, 2010
```
explicit handling of the instructions referencing it from the MC code
emitter.

llvm-svn: 116367
```
  12e493ac
- Refactor some of the encoding logic into a base class. This keeps us from having · 42200bca
  Bill Wendling authored Oct 12, 2010
```
to add 10+ lines to every instruction.

It may turn out that we can move this base class into it's parent class.

llvm-svn: 116362
```
  42200bca
- Add custom encoder for the 's' bit denoting whether an ARM arithmetic · d9d31daf
  Jim Grosbach authored Oct 12, 2010
```
instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.

llvm-svn: 116360
```
  d9d31daf
- Add encoding for VSUB and VCMP. · 646a5067
  Bill Wendling authored Oct 12, 2010
```
Fear not! I'm going to try a refactoring right now. :)

llvm-svn: 116359
```
  646a5067
- Encoding for VADDD. Plus a test for the VFP instructions. · ac6cd007
  Bill Wendling authored Oct 12, 2010
```
llvm-svn: 116348
```
  ac6cd007
- Split out the "size" field from the encoding. The newer documentation has it as · 98c29d73
  Bill Wendling authored Oct 12, 2010
```
a separate bit in the coding.

llvm-svn: 116347
```
  98c29d73
Oct 12, 2010
- Fix thinko in arm fast isel alloca rewrite. · 22e051ee
  Eric Christopher authored Oct 12, 2010
```
llvm-svn: 116339
```
  22e051ee
- Encoding for ARM-mode VADD.F32 instruction. · 576640f0
  Jim Grosbach authored Oct 12, 2010
```
llvm-svn: 116338
```
  576640f0
- Add MOVi ARM encoding. · 0e57a9f7
  Jim Grosbach authored Oct 12, 2010
```
llvm-svn: 116321
```
  0e57a9f7
- Nuke unused wrapper function. · feeae27a
  Jim Grosbach authored Oct 12, 2010
```
llvm-svn: 116318
```
  feeae27a
- Add encoding information for the remainder of the generic arithmetic · 6fead930
  Jim Grosbach authored Oct 12, 2010
```
ARM instructions.

llvm-svn: 116313
```
  6fead930
- PR8359: The ARM backend may end up allocating registers D16 to D31 when · dd6eb5b5
  Bob Wilson authored Oct 12, 2010
```
"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers.  Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!

llvm-svn: 116310
```
  dd6eb5b5
- Rework alloca handling so that we can load or store from casted · 7cd5cda6
  Eric Christopher authored Oct 12, 2010
```
address that we've looked through.

Fixes compilation problems in tramp3d from earlier patch.

llvm-svn: 116296
```
  7cd5cda6
- Handle a wider arrangement of loads. · db3bcc99
  Eric Christopher authored Oct 12, 2010
```
llvm-svn: 116284
```
  db3bcc99
- More ARM scheduling itinerary fixes. · e790afcb
  Evan Cheng authored Oct 11, 2010
```
llvm-svn: 116266
```
  e790afcb
- MC machine encoding for simple aritmetic instructions that use a shifted · b7c2962d
  Jim Grosbach authored Oct 11, 2010
```
register operand.

llvm-svn: 116259
```
  b7c2962d
- Second set of ARM/MC/ELF changes. · 109ff296
  Jason W Kim authored Oct 11, 2010
```
Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)

llvm-svn: 116257
```
  109ff296
- Proper VST scheduling itineraries. · 94ad008b
  Evan Cheng authored Oct 11, 2010
```
llvm-svn: 116251
```
  94ad008b
- Use a sane mechanism for that assert. · d42340ec
  Eric Christopher authored Oct 11, 2010
```
llvm-svn: 116249
```
  d42340ec
Oct 11, 2010
- We're not going to handle dynamic allocas anywhere else. · 72b91c17
  Eric Christopher authored Oct 11, 2010
```
llvm-svn: 116240
```
  72b91c17
- Make sure that the call stack adjustments have default operands. Also · 71ef1af6
  Eric Christopher authored Oct 11, 2010
```
leave custom lowerings for later.

Fixes some nightly tests.

llvm-svn: 116232
```
  71ef1af6
- Found a bug turning this on by default. Disable again for now. · e2a0b684
  Eric Christopher authored Oct 11, 2010
```
llvm-svn: 116220
```
  e2a0b684
- Fix help text. · 46cc854e
  Eric Christopher authored Oct 11, 2010
```
llvm-svn: 116218
```
  46cc854e
- Change flag from Enable to Disable since we're enabled by default. · 5501b7e8
  Eric Christopher authored Oct 11, 2010
```
Also don't use fast-isel on non-darwin since it's untested.

llvm-svn: 116217
```
  5501b7e8
- More binary encoding stuff, taking advantage of the new "by name" operand · 5476a274
  Jim Grosbach authored Oct 11, 2010
```
matching in tblgen to do the predicate operand.

llvm-svn: 116213
```
  5476a274
- Turn on arm fast isel by default. · 2276e87a
  Eric Christopher authored Oct 11, 2010
```
llvm-svn: 116212
```
  2276e87a
- MSVC hangs on compilation of ARMDisassembler.cpp. PR6866 applied to ARM target. · 0f5bfd27
  Francois Pichet authored Oct 11, 2010
```
llvm-svn: 116201
```
  0f5bfd27
- Copy and pasteo. · e1bcb43b
  Eric Christopher authored Oct 11, 2010
```
llvm-svn: 116198
```
  e1bcb43b
- Whitespace cleanup in ARM fast isel. · 7ac602bc
  Eric Christopher authored Oct 11, 2010
```
llvm-svn: 116197
```
  7ac602bc
- Add srem libcall support to ARM fast isel. · eae1b385
  Eric Christopher authored Oct 11, 2010
```
llvm-svn: 116196
```
  eae1b385
- Add i8 sdiv support for ARM fast isel. · e11017c1
  Eric Christopher authored Oct 11, 2010
```
llvm-svn: 116195
```
  e11017c1
- Implement select handling for ARM fast-isel. · 511aa319
  Eric Christopher authored Oct 11, 2010
```
llvm-svn: 116194
```
  511aa319
Oct 09, 2010
- Add VLD4 scheduling itineraries. · d7a404d8
  Evan Cheng authored Oct 09, 2010
```
llvm-svn: 116143
```
  d7a404d8
- Finish vld3 and vld4. · a762400b
  Evan Cheng authored Oct 09, 2010
```
llvm-svn: 116140
```
  a762400b
- Complete vld2 instruction itineries. · 4187f494
  Evan Cheng authored Oct 09, 2010
```
llvm-svn: 116136
```
  4187f494
- Multiply instructions are issued on pipeline 0. They do not need to reserve pipeline 1. · 1c7fa43e
  Evan Cheng authored Oct 09, 2010
```
llvm-svn: 116135
```
  1c7fa43e
- Correct some load / store instruction itinerary mistakes: · 05f13e94
  Evan Cheng authored Oct 09, 2010
```
1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.

llvm-svn: 116134
```
  05f13e94
- Check to make sure that the iterator isn't at the beginning of the basic block · 59ebe440
  Bill Wendling authored Oct 09, 2010
```
before decrementing. <rdar://problem/8529919>

llvm-svn: 116126
```
  59ebe440