cases, it's much nicer and more informative reading the alias.

llvm-svn: 129497

the alias".

llvm-svn: 129485

During post-legalization DAG combining, be careful to only create shifts where the RHS is of the legal type for the new operation.

llvm-svn: 129484

rdar://problem/9280370

llvm-svn: 129480

the same allocation size but different primitive sizes(e.g., <3xi32> and
<4xi32>).  When ScalarRepl promotes them, it can't use a bit cast but
should use a shuffle vector instead.

llvm-svn: 129472

Check for unallocated instruction encodings when disassembling Thumb Branch instructions (tBcc and t2Bcc).

rdar://problem/9280470

llvm-svn: 129471

rdar://problem/9279440

llvm-svn: 129469

llvm-svn: 129468

ignored. There was a test to catch this, but it was just blindly updated in
a large change. This fixes another part of <rdar://problem/9275290>.

llvm-svn: 129466

llvm-svn: 129463

rdar://problem/9276651

llvm-svn: 129462

Remove extra bytes that were added for gdb.  We do not have good poiner to understand actual reason behind this fixme. Spot checking suggest that newer gdb does not need this.

llvm-svn: 129461

rdar://problem/9276427

llvm-svn: 129456

llvm-svn: 129451

llvm-svn: 129450

Passing unroll parameters (unroll-count, threshold, and partial unroll) via LoopUnroll class's ctor. Doing so 
will allow multiple context with different loop unroll parameters to run.  This is a minor change and no effect 
on existing application.

llvm-svn: 129449

llvm-svn: 129447

llvm-svn: 129445

related tweaks to ExprMapKeyType.

llvm-svn: 129443

llvm-svn: 129442

llvm-svn: 129441

llvm-svn: 129439

llvm-svn: 129435

the max itself, so it is not easy to write a test case for this, but I added a
test case that would fail if the code in AsmPrinter were removed.

llvm-svn: 129432

llvm-svn: 129429

alignment for its type, use the minimum of the specified alignment and the ABI
alignment. This fixes <rdar://problem/9275290>.

llvm-svn: 129428

Additional fixes:
Do something reasonable for subtargets with generic
itineraries by handle node latency the same as for an empty
itinerary. Now nodes default to unit latency unless an itinerary
explicitly specifies a zero cycle stage or it is a TokenFactor chain.

Original fixes:
UnitsSharePred was a source of randomness in the scheduler: node
priority depended on the queue data structure. I rewrote the recent
VRegCycle heuristics to completely replace the old heuristic without
any randomness. To make the ndoe latency adjustments work, I also
needed to do something a little more reasonable with TokenFactor. I
gave it zero latency to its consumers and always schedule it as low as
possible.

llvm-svn: 129421

llvm-svn: 129419

llvm-svn: 129417

Implement the ones that were missing in the asm streamer.

llvm-svn: 129413

rdar://problem/9273947

llvm-svn: 129411

The ARMARM specifies these instructions as unpredictable when storing the
writeback register. This shouldn't affect code generation much since storing a
pointer to itself is quite rare.

llvm-svn: 129409

registers for fast allocation.

Fixes rdar://9207598

llvm-svn: 129408

llvm-svn: 129407

llvm-svn: 129406

llvm-svn: 129405

llvm-svn: 129403

This mechanical patch moves type handling into CompileUnit from DwarfDebug. In case of multiple compile unit in one object file, each compile unit is responsible for its own set of type entries anyway. This refactoring makes this obvious.

llvm-svn: 129402

Now that we have a first-class way to represent unaligned loads, the unaligned
load intrinsics are superfluous.

First part of <rdar://problem/8460511>.

llvm-svn: 129401

llvm-svn: 129400