llvm-svn: 132424

types if the vector type is legal.

Fixes rdar://9306086

llvm-svn: 132420

llvm-svn: 132419

the TargetLowering enum.

llvm-svn: 132418

llvm-svn: 132416

This commit caused regressions in i386 flops-[568], matrix, salsa20,
256.bzip2, and enc-md5.

llvm-svn: 132413

rdar://problem/5660695

llvm-svn: 132411

floating-point comparison, generate a mask of 0s or 1s, and generally
DTRT with NaNs.  Only profitable when the user wants a materialized 0
or 1 at runtime.  rdar://problem/5993888

llvm-svn: 132404

llvm-svn: 132402

Add TargetRegisterInfo::hasSubClassEq and use it to check for compatible
register classes instead of trying to list all register classes in
X86's getLoadStoreRegOpcode.

llvm-svn: 132398

llvm-svn: 132396

llvm-svn: 132395

This patch is another step in the direction of adding vector select. In this
patch we add a flag to enable a new type legalization decision - to promote
integer elements in vectors. Currently, the rest of the codegen does not support
this kind of legalization.  This flag will be removed when the transition is
complete.

llvm-svn: 132394

patch to TargetLowering.cpp.  rdar://problem/5660695

llvm-svn: 132388

For targets with no itinerary (x86) it is a nop by default. For
targets with issue width already expressed in the itinerary (ARM) it
bypasses a scoreboard check but otherwise does not affect the
schedule. It does make the code more consistent and complete and
allows new targets to specify their issue width in an arbitrary way.

llvm-svn: 132385

landing pad, forward llvm.eh.resume calls to it instead of turning them
invalidly into invokes.

llvm-svn: 132382

turns out that it could cause an infinite loop in some situations. If this code
is triggered and it converts a cleanup into a catchall, but that cleanup was in
already in a cleanup, then the _Unwind_SjLj_Resume could infinite loop. I.e.,
the code doesn't consume the exception object and passes it on to
_Unwind_SjLj_Resume. But _USjLjR expects it to be consumed (since it's landing
at a catchall instead of a cleanup). So it uses the values that are presently
there, which are the values that tell it to jump to the fake landing pad.
<rdar://problem/9508402>

llvm-svn: 132381

llvm-svn: 132377

llvm-svn: 132373

llvm-svn: 132371

so that their sign extended forms are congruent when no overflow occurs.

llvm-svn: 132360

When assigned ranges are evicted, they are put in the RS_Evicted stage and are
not allowed to evict anything else. That prevents looping automatically.

When evicting ranges just to get a cheaper register, use only spill weights to
find the possible candidates. Avoid breaking hints for this purpose, it is not
worth it.

Start implementing more complex eviction heuristics, guarded by the temporary
-complex-eviction flag. The initial version permits a heavier range to be
evicted if it doesn't have any uses where the evicting range is live. This makes
it a good candidate for live ranfge splitting.

llvm-svn: 132358

llvm.memcpy.* has two distinct associated address spaces; the source address space, and the destination address space.  Fix up the interface on MemIntrinsic and MemTransferInst to make this clear, and fix InstructionDereferencesPointer in LazyValueInfo.cpp to use the interface properly.

llvm-svn: 132356

llvm-svn: 132355

llvm-svn: 132353

llvm-svn: 132351

sub with a non-constant.  Fix comments, enlarge test case.
rdar://problem/6501862

llvm-svn: 132348

llvm-svn: 132341

llvm-svn: 132340

llvm-svn: 132336

must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.

llvm-svn: 132324

nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions.
The intrinsics are implemented by creating pseudo-instructions, which are
then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter.

Patch by Sasa Stankovic.

llvm-svn: 132323

Dynamic, Initial Exec and Local Exec TLS models.

Patch by Sasa Stankovic

llvm-svn: 132322

directives.

Fixes PR9826.

llvm-svn: 132317

rdar://problem/6501862

llvm-svn: 132316

llvm-svn: 132315

same dwarf number. This will be used for creating a dwarf number to register
mapping.

The only case that needs this so far is the XMM/YMM registers that unfortunately
do have the same numbers.

llvm-svn: 132314

subregisters of the 64 bit ones.

llvm-svn: 132313

and for now the generic dwarf emission will automatically use the superregister
numbers.

llvm-svn: 132312

llvm-svn: 132309