should work for intel long double, but ppc long double aborts
in convert.

llvm-svn: 57672

use a SUB instruction instead of an ADD, because -128 can be
encoded in an 8-bit signed immediate field, while +128 can't be.
This avoids the need for a 32-bit immediate field in this case.

A similar optimization applies to 64-bit adds with 0x80000000,
with the 32-bit signed immediate field.

To support this, teach tablegen how to handle 64-bit constants.

llvm-svn: 57663

shift counts, and patterns that match dynamic shift counts
when the subtract is obscured by a truncate node.

Add DAGCombiner support for recognizing rotate patterns
when the shift counts are defined by truncate nodes.

Fix and simplify the code for commuting shld and shrd
instructions to work even when the given instruction doesn't
have a parent, and when the caller needs a new instruction.

These changes allow LLVM to use the shld, shrd, rol, and ror
instructions on x86 to replace equivalent code using two
shifts and an or in many more cases.

llvm-svn: 57662

llvm-svn: 57660

llvm-svn: 57649

llvm-svn: 57644

using the 'volatile' qualifier. This should not have any operational consequences
on code, because tags should always be stripped off (giving a non-volatile pointer)
before dereferencing. The new qualification is there to catch some attempts to use
tagged pointers in a context where an untagged pointer is appropriate.

Notably this approach does not catch dereferencing of tagged pointers, but helps
in separating the two concepts a bit.

llvm-svn: 57641

uninitialized in these functions with gcc-4.3.

llvm-svn: 57635

warning on x86-64 with gcc-4.3.

llvm-svn: 57634

llvm-svn: 57631

x86 backend.  These will all be answered with "patches welcome", so
a PR doesn't help drive them along.

llvm-svn: 57630

basically working, feel free to remove the tag.  The other targets have
really basic things that break them.

llvm-svn: 57628

llvm-svn: 57626

llvm-svn: 57625

llvm-svn: 57622

llvm-svn: 57621

additional information in Loads, Stores, Calls, Invokes,
InsertValueInsts, and ExtractValueInsts.

llvm-svn: 57620

llvm-svn: 57618

because it declares a std::vector<MachineMove>, and strict
concept checking requires the definition of MachineMove to be
available.

llvm-svn: 57617

computation. A def of a register doesn't necessarily kill
live super-registers.

llvm-svn: 57614

an unindexed load.

llvm-svn: 57612

to find opportunities for store-to-load forwarding or load CSE,
in the same way that visitStore scans back to do DSE. Also, define
a new helper function for testing whether the addresses of two
memory accesses are known to have the same value, and use it in
both visitStore and visitLoad.

These two changes allow instcombine to eliminate loads in code
produced by front-ends that frequently emit obviously redundant
addressing for memory references.

llvm-svn: 57608

llvm-svn: 57606

llvm-svn: 57595

llvm-svn: 57594

This fixes PR2894.

llvm-svn: 57589

llvm-svn: 57586

llvm-svn: 57582

llvm-svn: 57579

llvm-svn: 57577

llvm-svn: 57576

llvm-svn: 57575

llvm-svn: 57574

llvm-svn: 57573

llvm-svn: 57572

the predicates by extending simple predicates to create
more complex predicates instead of duplicating the logic
for the simple predicates.

This doesn't reduce much redundancy in DAGISelEmitter.cpp's
generated source yet; that will require improvements to
DAGISelEmitter.cpp's instruction sorting, to make it more
effectively group nodes with similar predicates together.

llvm-svn: 57565

llvm-svn: 57561

integer type.  Invalid things like 'float 42' are now rejected by the
semantic analysis in the productions not the parser.  This fixes PR2733.

llvm-svn: 57560

llvm-svn: 57559

INTTYPE everywhere.

llvm-svn: 57558