MachineOperand auxInfo. Previous clunky implementation uses an external map
to track sub-register uses. That works because register allocator uses
a new virtual register for each spilled use. With interval splitting (coming
soon), we may have multiple uses of the same register some of which are
of using different sub-registers from others. It's too fragile to constantly
update the information.

llvm-svn: 44104

from a file containing Function/BasicBlock pairings. This is not safe against
anonymous or abnormally-named Funcs or BBs.

Make bugpoint use this interface to pass the BBs list to the child bugpoint.

llvm-svn: 44101

by inserting unreachable after no-return calls.

llvm-svn: 44099

llvm-svn: 44097

patch on friday.

llvm-svn: 44068

interference.

llvm-svn: 44064

llvm-svn: 44063

llvm-svn: 44057

to use different mappings for EH and debug info;
no functional change yet.
Fix warning in X86CodeEmitter.

llvm-svn: 44056

llvm-svn: 44048

llvm-svn: 44045

and simplifycfg in the rare cases when it is needed.

llvm-svn: 44044

adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).

This can only result in tears...

llvm-svn: 44037

some regressions on ppc nightly tests.

llvm-svn: 44029

Fixed some AsmPrinter issues
Added GLOBAL_OFFSET_TABLE Node handle.

llvm-svn: 44024

clients of the Deserializer to read the pointer ID before they are ready
to deserialize the object (which can mean registering a pointer reference
with the backpatcher).

Changed some methods that took an argument "SerializedPtrID" to "const SerializedPtrID&" (pass-by-reference).  This is to accommodate a future
revision of SerializedPtrID where it may be much fatter than an unsigned
integer.

llvm-svn: 44021

llvm-svn: 44019

Target maintainers: please check that the instructions for your target are correctly marked.

llvm-svn: 44012

llvm-svn: 44010

to be a pass of its own.  Instead, move it out into a helper method.

llvm-svn: 44002

llvm-svn: 43998

This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,

llvm-svn: 43997

dealing with types whose size & alignment are
different on different subtargets.  Use it for x86 f80.

llvm-svn: 43988

llvm-svn: 43982

llvm-svn: 43978

serialized block in the bitstream, including a block in an entirely different
nesting than the current block. This is useful for deserializing objects from
a bitstream in an order different from the order that they were serialized.

llvm-svn: 43973

llvm-svn: 43960

llvm-svn: 43955

llvm-svn: 43954

llvm-svn: 43950

fixes a crash on Transforms/GlobalOpt/2007-11-09-GEP-GEP-Crash.ll and 
rdar://5585488.

llvm-svn: 43949

llvm-svn: 43944

llvm-svn: 43941

llvm-svn: 43940

llvm-svn: 43939

apints on big-endian machines if the bitwidth is
not a multiple of 8.  Introduce a new helper,
MVT::getStoreSizeInBits, and use it.

llvm-svn: 43934

llvm-svn: 43933

Then:
        call    "L1$pb"
"L1$pb":
        popl    %eax
		...
LBB1_1: # entry
        imull   $4, %ecx, %ecx
        leal    LJTI1_0-"L1$pb"(%eax), %edx
        addl    LJTI1_0-"L1$pb"(%ecx,%eax), %edx
        jmpl    *%edx

        .align  2
        .set L1_0_set_3,LBB1_3-LJTI1_0
        .set L1_0_set_2,LBB1_2-LJTI1_0
        .set L1_0_set_5,LBB1_5-LJTI1_0
        .set L1_0_set_4,LBB1_4-LJTI1_0
LJTI1_0:
        .long    L1_0_set_3
        .long    L1_0_set_2

Now:
        call    "L1$pb"
"L1$pb":
        popl    %eax
		...
LBB1_1: # entry
        addl    LJTI1_0-"L1$pb"(%eax,%ecx,4), %eax
        jmpl    *%eax

		.align  2
		.set L1_0_set_3,LBB1_3-"L1$pb"
		.set L1_0_set_2,LBB1_2-"L1$pb"
		.set L1_0_set_5,LBB1_5-"L1$pb"
		.set L1_0_set_4,LBB1_4-"L1$pb"
LJTI1_0:
        .long    L1_0_set_3
        .long    L1_0_set_2

llvm-svn: 43924

llvm-svn: 43923

llvm-svn: 43922