- Apr 12, 2012
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Akira Hatanaka authored
Invalid operation is signaled if the operand of these instructions is NaN. llvm-svn: 154545
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Kevin Enderby authored
of a VST instruction. llvm-svn: 154544
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Akira Hatanaka authored
- FCOPYSIGN nodes that have operands of different types were not handled. - Different code was generated depending on the endianness of the target. Additionally, code is added that emits INS and EXT instructions, if they are supported by target (they are R2 instructions). llvm-svn: 154540
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- Apr 11, 2012
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Jim Grosbach authored
llvm-svn: 154533
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Jim Grosbach authored
llvm-svn: 154532
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Jim Grosbach authored
llvm-svn: 154531
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Benjamin Kramer authored
llvm-svn: 154527
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Chad Rosier authored
llvm-svn: 154522
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Andrew Trick authored
llvm-svn: 154518
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Jim Grosbach authored
While there is an encoding for it in VUZP, the result of that is undefined, so we should avoid it. Define the instruction as a pseudo for VTRN.32 instead, as the ARM ARM indicates. rdar://11222366 llvm-svn: 154511
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Andrew Trick authored
The pruning is more complete if it is not done incrementally. The code is also a tad less convluted. llvm-svn: 154510
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Jim Grosbach authored
While there is an encoding for it in VZIP, the result of that is undefined, so we should avoid it. Define the instruction as a pseudo for VTRN.32 instead, as the ARM ARM indicates. rdar://11221911 llvm-svn: 154505
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Sylvestre Ledru authored
Thanks to Pino Toscano for the patch llvm-svn: 154500
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Benjamin Kramer authored
FoldingSet is implemented as a chained hash table. When there is a hash collision during insertion, which is common as we fill the table until a load factor of 2.0 is hit, we walk the chained elements, comparing every operand with the new element's operands. This can be very expensive if the MDNode has many operands. We sacrifice a word of space in MDNode to cache the full hash value, reducing compares on collision to a minimum. MDNode grows from 28 to 32 bytes + operands on x86. On x86_64 the new bits fit nicely into existing padding, not growing the struct at all. The actual speedup depends a lot on the test case and is typically between 1% and 2% for C++ code with clang -c -O0 -g. llvm-svn: 154497
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Benjamin Kramer authored
llvm-svn: 154496
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Benjamin Kramer authored
llvm-svn: 154495
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Nadav Rotem authored
llvm-svn: 154494
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Duncan Sands authored
binary and assembly. Patch by Carlo Kok. Emitting was inspired by but not based on the D llvm bindings. llvm-svn: 154493
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Chandler Carruth authored
Yea, 'NumCallerCallersAnalyzed' isn't a great name, suggestions welcome. llvm-svn: 154492
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Nadav Rotem authored
Fix a dagcombine optimization which assumes that the vsetcc result type is always of the same size as the compared values. This is ture for SSE/AVX/NEON but not for all targets. llvm-svn: 154490
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Duncan Sands authored
llvm-svn: 154488
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Nadav Rotem authored
Original message: Modify the code that lowers shuffles to blends from using blendvXX to vblendXX. blendV uses a register for the selection while Vblend uses an immediate. On sandybridge they still have the same latency and execute on the same execution ports. llvm-svn: 154483
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Evan Cheng authored
predicates. Also remove NEON2 since it's not really useful and it is confusing. If NEON + VFP4 implies NEON2 but NEON2 doesn't imply NEON + VFP4, what does it really mean? rdar://10139676 llvm-svn: 154480
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Craig Topper authored
llvm-svn: 154479
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Craig Topper authored
llvm-svn: 154478
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Andrew Trick authored
llvm-svn: 154477
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Andrew Trick authored
Handle mixing allocatable and unallocatable register gracefully. Simplify the pruning of register unit sets. llvm-svn: 154474
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Craig Topper authored
llvm-svn: 154473
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Charles Davis authored
ret instructions. llvm-svn: 154468
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Evan Cheng authored
llvm-svn: 154466
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Kevin Enderby authored
for all opcodes handed by DecodeVLDInstruction() in ARMDisassembler.cpp . llvm-svn: 154459
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Jim Grosbach authored
rdar://11222742 llvm-svn: 154457
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Evan Cheng authored
1. The new instruction itinerary entries are not properly described. 2. The asm parser can't handle vfms and vfnms. 3. There were no assembler, disassembler test cases. 4. HasNEON2 has the wrong assembler predicate. rdar://10139676 llvm-svn: 154456
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Jakob Stoklund Olesen authored
Allow cheap instructions to be hoisted if they are register pressure neutral or better. This happens if the instruction is the last loop use of another virtual register. Only expensive instructions are allowed to increase loop register pressure. llvm-svn: 154455
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Jakob Stoklund Olesen authored
Hoisting a value that is used by a PHI in the loop will introduce a copy because the live range is extended to cross the PHI. The same applies to PHIs in exit blocks. Also use this opportunity to make HasLoopPHIUse() non-recursive. llvm-svn: 154454
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Jakob Stoklund Olesen authored
llvm-svn: 154453
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Andrew Trick authored
llvm-svn: 154452
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Owen Anderson authored
Move the constant-folding support for FP_ROUND in SelectionDAG from the one-operand version of getNode() to the two-operand version, since it became a two-operand node at sound point. Zap a testcase that this allows us to completely fold away. llvm-svn: 154447
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