llvm-svn: 11535

llvm-svn: 11517

llvm-svn: 11515

MRegisterInfo::getNumRegs() instead of
MRegisterInfo::FirstVirtualRegister.

Also use MRegisterInfo::is{Physical,Virtual}Register where
appropriate.

llvm-svn: 11477

llvm-svn: 11393

Whitespace cleanups.

llvm-svn: 11389

ilist of MachineInstr objects. This allows constant time removal and
insertion of MachineInstr instances from anywhere in each
MachineBasicBlock. It also allows for constant time splicing of
MachineInstrs into or out of MachineBasicBlocks.

llvm-svn: 11340

llvm-svn: 11283

llvm-svn: 11278

the Virt2PhysRegMap std::map with an std::vector.  This speeds up the
register allocator another (almost) 40%, from .72->.45s in a release build
of LLC on 253.perlbmk.

llvm-svn: 11219

from physical registers, and they are always dense, it makes sense to not have
a ton of RBtree overhead.  This change speeds up regalloclocal about ~30% on
253.perlbmk, from .35s -> .27s in the JIT (in LLC, it goes from .74 -> .55).

Now live variable analysis is the slowest codegen pass.  Of course it doesn't
help that we have to run it twice, because regalloclocal doesn't update it,
but even if it did it would be the slowest pass (now it's just the 2x slowest
pass :(

llvm-svn: 11215

method

llvm-svn: 11037

when an implicitely defined register is later used by an alias. For example:

         call foo
         %reg1024 = mov %AL

The call implicitely defines EAX but only AL is used. Before this fix
no information was available on AL. Now EAX and all its aliases except
AL get defined and die at the call instruction whereas AL lives to be
killed by the assignment.

llvm-svn: 10813

instead, since this pass doesn't expose any state to its users.

llvm-svn: 10520

llvm-svn: 10513

    a) remove opIsUse(), opIsDefOnly(), opIsDefAndUse()
    b) add isUse(), isDef()
    c) rename opHiBits32() to isHiBits32(),
              opLoBits32() to isLoBits32(),
              opHiBits64() to isHiBits64(),
              opLoBits64() to isLoBits64().

This results to much more readable code, for example compare
"op.opIsDef() || op.opIsDefAndUse()" to "op.isDef()" a pattern used
very often in the code.

llvm-svn: 10461

llvm-svn: 10444

this point, the second operand must be a physical register (it cannot
be a virtual one).

llvm-svn: 10292

llvm-svn: 9903

llvm-svn: 9496

Header files will be on the way.

llvm-svn: 9298

and TargetInstrDescriptor::ImplicitUses to always point to a null
terminated array and never be null. So there is no need to check for
pointer validity when iterating over those sets. Code that looked
like:

if (const unsigned* AS = TID.ImplicitDefs) {
  for (int i = 0; AS[i]; ++i) {
    // use AS[i]
  }
}

was changed to:

for (const unsigned* AS = TID.ImplicitDefs; *AS; ++AS) {
  // use *AS
}

llvm-svn: 8960

llvm-svn: 8095

llvm-svn: 7916

llvm-svn: 7906

llvm-svn: 7823

llvm-svn: 7591

llvm-svn: 7588

llvm-svn: 7584

* Add a lot more DEBUG output, which is better structured than before
* Fix bug: Jello/2003-08-04-PhysRegLiveFailure.llx

llvm-svn: 7583

llvm-svn: 7533

llvm-svn: 7503

llvm-svn: 7497

    Fixed spilling of %fcc[0-3] which are part of %fsr.

(2) Moved some machine-independent reg-class code to class TargetRegInfo
    from SparcReg{Class,}Info.

(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
    and related functions and flags.  Fixed several bugs where only
    "isDef" was being checked, not "isDefAndUse".

llvm-svn: 6341

llvm-svn: 6109

llvm-svn: 6002

llvm-svn: 5326

llvm-svn: 5272

* Convert to use PHIElimination pass
* Don't spill values which have just been reloaded (big win reducing spills)
* Add experimental support for eliminating spills before TwoAddress
  instructions.  It currently is broken so it is #ifdef'd out.
* Use new "is terminator" flag on instructions instead of looking for
  branches and returns explicitly.

llvm-svn: 5219

llvm-svn: 5200