This will prevent breakage when I introduce the DecayedType sugar node.

llvm-svn: 184755

[PowerPC] Add predicted forms of branches

This adds support for the predicted forms of branches (+/-).
There are three cases to consider:
- Branches using a PPC::Predicate code
  For these, I've added new PPC::Predicate codes corresponding
  to the BO values for predicted branch forms, and updated insn
  printing to print them correctly.  I've also added new aliases
  for the asm parser matching the new forms.
- bt/bf
  I've added new aliases matching to gBC etc.
- bd(n)z variants
  I've added new instruction patterns for the predicted forms.

In all cases, the new patterns are used for the asm parser only.
(The new infrastructure ought to be sufficient to allow use by
the compiler too at some point.)

llvm-svn: 184754

llvm-svn: 184753

currently it episodically fails
the hypothesis it is due to racy race detection algorithm
the sleep should make it more robust

llvm-svn: 184752

print-size-type.cpp was checking for specific record layout output for invalid
decls; I've removed the checks but left the records as tests for not crashing.

llvm-svn: 184751

llvm-svn: 184750

llvm-svn: 184749

llvm-svn: 184748

now it includes proper functions (including interceptors)
and does not include local functions that lead to build failures

llvm-svn: 184747

- Sort functions in the same order
- Match whitespace
- Remove commetned out code
- Make filename in comments match filename

llvm-svn: 184746

llvm-svn: 184745

llvm-svn: 184744

llvm-svn: 184743

Akin to r181712 (88e529b7) of Linux/ProcessMonitor.cpp

llvm-svn: 184742

Revision r147613 (2341d35) renamed this file with s/Linux/POSIX/, but
header guards and comments were not updated to match.

llvm-svn: 184741

CheckParmForFunctionDef performs standard checks for type completeness
and other things like a destructor check for the MSVC++ ABI.

llvm-svn: 184740

llvm-svn: 184739

Using offsetof to an item within an array is an extension so mark it as such to avoid compiler warnings.

llvm-svn: 184738

llvm-svn: 184737

llvm-svn: 184736

llvm-svn: 184735

This an entry point from uninstrumented code.

llvm-svn: 184734

Since r181446 the m_private_run_lock has been used for all platforms.

llvm-svn: 184733

All of LLVM's Python scripts only support Python 2 for widely understood
reasons.

Patch by Yonggang Luo.

llvm-svn: 184732

llvm-svn: 184731

llvm-svn: 184730

llvm-svn: 184729

NVPTXTargetObjectFile.h: Initialize some pointers as NULL in the constructor of NVPTXTargetObjectFile. ~NVPTXTargetObjectFile() tries to delete them.

It caused crash on some hosts since r184595.

llvm-svn: 184728

FIXME: A couple of tests have been suppressed.
I know it'd be bad with _MSC_VER here, though.

llvm-svn: 184727

llvm-svn: 184726

[PowerPC] Add t/f branch mnemonics to asm parser

This adds the bt/bf/bd(n)zt/bd(n)zf mnemonics as aliases for the
asm parser, resolving to the generic conditional patterns.

llvm-svn: 184725

This should hopefully have fixed the stage2/stage3 miscompare on the dragonegg
testers.

"LoopVectorize: Use the dependence test utility class

We now no longer need alias analysis - the cases that alias analysis would
handle are now handled as accesses with a large dependence distance.

We can now vectorize loops with simple constant dependence distances.

  for (i = 8; i < 256; ++i) {
    a[i] = a[i+4] * a[i+8];
  }

  for (i = 8; i < 256; ++i) {
    a[i] = a[i-4] * a[i-8];
  }

We would be able to vectorize about 200 more loops (in many cases the cost model
instructs us no to) in the test suite now. Results on x86-64 are a wash.

I have seen one degradation in ammp. Interestingly, the function in which we
now vectorize a loop is never executed so we probably see some instruction
cache effects. There is a 2% improvement in h264ref. There is one or the other
TSCV loop kernel that speeds up.

radar://13681598"

llvm-svn: 184724

We are creating the runtime checks using this set so we need a deterministic
iteration order.

llvm-svn: 184723

[PowerPC] Support generic conditional branches in asm parser

This adds instruction patterns to cover the generic forms of
the conditional branch instructions.  This allows the assembler
to support the generic mnemonics.

The compiler will still generate the various specific forms
of the instruction that were already supported.

llvm-svn: 184722

[PowerPC] Support absolute branches

There is currently only limited support for the "absolute" variants
of branch instructions.  This patch adds support for the absolute
variants of all branches that are currently otherwise supported.

This requires adding new fixup types so that the correct variant
of relocation type can be selected by the object writer.

While the compiler will continue to usually choose the relative
branch variants, this will allow the asm parser to fully support
the absolute branches, with either immediate (numerical) or
symbolic target addresses.

No change in code generation intended.

llvm-svn: 184721

[PowerPC] Support bd(n)zl and bd(n)zlrl

This adds support for the bd(n)zl and bd(n)zlrl instructions.
The patterns are currently used for the asm parser only.

llvm-svn: 184720

[PowerPC] Support b(cond)l in the asm parser

This patch adds support for the conditional variants of bl.
The pattern is currently used by the asm parser only.

llvm-svn: 184719

[PowerPC] Support blrl and variants in the asm parser

This patch adds support for blrl and its conditional variants.
The patterns are (currently) used for the asm parser only.

llvm-svn: 184718

llvm-svn: 184717

 This patch introduces RegisterOperand class into Mips FPU instruction definitions and adds dedicated parser methods to MipsAsmParser. It is the first in a series of patches that should fix the problems with parsing Mips FPU instructions and optimize the code in MipsAsmParser.

llvm-svn: 184716