AddLandingPadInfo takes a landingpad instruction and grabs all of the
information from it that it needs for EH table generation.

llvm-svn: 136429

LBH_TAKEN_WEIGHT + LBH_NONTAKEN_WEIGHT = 128 which in _most_ cases reduce
number of rounding errors.

llvm-svn: 136428

llvm-svn: 136427

masks an existing method in its primary class, class extensions,
and primary class's non-optional protocol methods; as primary
class, or one of its subclass's will implement this method.
This warning has potential of being noisy so it has its own
group.  // rdar://7020493

llvm-svn: 136426

llvm-svn: 136425

llvm-svn: 136424

Some documentation fixes so that we are explicit about which iteration order is source-order.  Also, removing unused NextInSource field of Module.

llvm-svn: 136423

Really remove FlatStoreManager and BasicStoreManager, this time from the driver.  Also remove associated tests.  Sorry for the messy commits; this is the result of a botched Git merge.

llvm-svn: 136422

llvm-svn: 136421

Remove FlatStoreManager and BasicStoreManager.  The latter has long been obsolete and the former has no had development in a long time.

llvm-svn: 136420

[analyzer] Overhaul how the static analyzer expects CFGs by forcing CFGs to be linearized only when used by the static analyzer.  This required a rewrite of LiveVariables, and exposed a ton of subtle bugs.

The motivation of this large change is to drastically simplify the logic in ExprEngine going forward.

Some fallout is that the output of some BugReporterVisitors is not as accurate as before; those will
need to be fixed over time.  There is also some possible performance regression as RemoveDeadBindings
will be called frequently; this can also be improved over time.

llvm-svn: 136419

[analyzer] fix bug in malloc checker where the tracked symbol would not properly be removed from the state.

llvm-svn: 136418

llvm-svn: 136417

[analyzer] Add StoreManager::includedInBindings() to to query whether a region is used in any bindings.

llvm-svn: 136416

llvm-svn: 136415

llvm-svn: 136414

llvm-svn: 136413

the proper expression.

llvm-svn: 136412

it appropriately. Also, patch up a place where we were failing to map
local macro definition IDs into global macro definition IDs.

llvm-svn: 136411

llvm-svn: 136410

llvm-svn: 136409

llvm-svn: 136408

Add parsing support for BLX (immediate). Since the register operand version is
predicated and the label operand version is not, we have to use some special
handling to get the operand list right for matching.

llvm-svn: 136406

llvm-svn: 136405

'atomicrmw' instructions, which allow representing all the current atomic
rmw intrinsics.

The allowed operands for these instructions are heavily restricted at the
moment; we can probably loosen it a bit, but supporting general
first-class types (where it makes sense) might get a bit complicated,
given how SelectionDAG works.

As an initial cut, these operations do not support specifying an alignment,
but it would be possible to add if we think it's useful. Specifying an
alignment lower than the natural alignment would be essentially
impossible to support on anything other than x86, but specifying a greater
alignment would be possible.  I can't think of any useful optimizations which
would use that information, but maybe someone else has ideas.

Optimizer/codegen support coming soon.

llvm-svn: 136404

llvm-svn: 136403

llvm-svn: 136402

Code like that would only be produced by bugpoint, but we should still
handle it correctly.

When a register is defined by a REG_SEQUENCE of undefs, the register
itself is undef. Previously, we would create a register with uses but no
defs.

Fixes part of PR10520.

llvm-svn: 136401

llvm-svn: 136400

Add parsing support that handles converting the lsb+width source into the
odd way we represent the instruction (an inverted bitfield mask).

llvm-svn: 136399

there is no frequency difference whether condition is in the header or in
the latch.

llvm-svn: 136398

llvm-svn: 136396

consistently in the ASTReader.

llvm-svn: 136395

by specifying your EXE make variable via your Makefile or within the Python test script.

llvm-svn: 136394

llvm-svn: 136392

IDs properly, although the mapping itself is still trivial.

llvm-svn: 136391

llvm-svn: 136390

llvm-svn: 136389

There are two conflicting strategies in play:

- Under high register pressure, we want to assign large live ranges
  first. Smaller live ranges are easier to place afterwards.

- Live range splitting is guided by interference, so splitting should be
  deferred until interference is as realistic as possible.

With the recent changes to the live range stages, and with compact
regions enabled, it is less traumatic to split a live range too early.
If some of the split products were too big, they can often be split
again.

By reversing the RS_Split order, we get this queue order:

1. Normal live ranges, large to small.
2. RS_Split live ranges, large to small.

The large-to-small order improves RAGreedy's puzzle solving skills under
high register pressure. It may cause a bit more iterated splitting, but
we handle that better now.

With this change, -compact-regions is mostly an improvement on SPEC.

llvm-svn: 136388

This should be the only code necessary for DWARF EH prepare.

llvm-svn: 136387