Fix a bug in spill weight computation. If the alias is a super-register, and the super-register is in the register class we are trying to allocate. Then add the weight to all sub-registers of the super-register even if they are not aliases.                                                                                                  
e.g. allocating for GR32, bh is not used, updating bl spill weight.                                                                                                        
     bl should get the same spill weight otherwise it will be choosen                                                                                              
     as a spill candidate since spilling bh doesn't make ebx available.
This fix PR2866.

llvm-svn: 67574

llvm-svn: 67565

same as a normal i80 {low64, high16} rather
than its own {high64, low16}.  A depressing number
of places know about this; I think I got them all.
Bitcode readers and writers convert back to the old
form to avoid breaking compatibility.

llvm-svn: 67562

llvm-svn: 67560

a data dependency on the load node, so it really needs a
data-dependence edge to the load node, even if the load previously
existed.

And add a few comments.

llvm-svn: 67554

llvm-svn: 67545

llvm-svn: 67544

actually have uses, which reflects the way it's used.

llvm-svn: 67540

in an SUnit, instead of just the first one. This fix is needed
by some upcoming scheduler changes.

llvm-svn: 67531

defs, regardless of whether they are actually used.

llvm-svn: 67528

explicitly flush it.

llvm-svn: 67526

llvm-svn: 67525

llvm-svn: 67524

llvm-svn: 67523

static member functions, and add getIncomingValueNumForOperand
and getIncomingBlockNumForOperand, which are the respective
inverses.

llvm-svn: 67522

llvm-svn: 67518

Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies.

llvm-svn: 67512

Do not fold away subreg_to_reg if the source register has a sub-register index. That means the source register is taking a sub-register of a larger register. e.g. On x86
%RAX<def> = ...
%RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3
The first def is defining RAX, not EAX so the top bits were not zero-extended.

llvm-svn: 67511

llvm-svn: 67510

were when we came around, not to their default handler.  This 
should fix PR3848

llvm-svn: 67509

llvm-svn: 67508

llvm-svn: 67507

llvm-svn: 67505

Do not recommend llvm::OStream anymore.  Use raw_ostream or MemoryBuffer.

llvm-svn: 67504

i8 return values.

llvm-svn: 67502

llvm-svn: 67500

llvm-svn: 67473

work.

llvm-svn: 67471

llvm-svn: 67469

llvm-svn: 67468

llvm-svn: 67458

llvm-svn: 67454

llvm-svn: 67451

unneeded bitcast is requested.  This is common for frontends who just unconditionally
cast even if the target is often the right type already.  THis prevents going into
getFoldedCast which switches on the opcode and does a bunch of other stuff before
doing the same opzn.

llvm-svn: 67435

tidy some df iteration stuff, patch by John Mosby!

llvm-svn: 67428

Handle odd registers allocation in FGR32.

llvm-svn: 67422

llvm-svn: 67416

llvm-svn: 67412

shifts together.  This fixes PR3851.

llvm-svn: 67411

linkage: the value may be replaced with something
different at link time.  (Frontends that want to
allow values to be loaded out of weak constants can
give their constants weak_odr linkage).

llvm-svn: 67407