llvm-svn: 24139

need to send chris, jim and sampo a box of fish each

llvm-svn: 24135

one sometimes needs to pass FP args in both FP *and* integer registers.

llvm-svn: 24134

clever little tablegen!

llvm-svn: 24133

llvm-svn: 24132

llvm-svn: 24131

llvm-svn: 24130

not compiling a whole program at a time :)

llvm-svn: 24129

llvm-svn: 24118

llvm-svn: 24110

llvm-svn: 24109

llvm-svn: 24107

llvm-svn: 24096

DAG instruction selector, which should be destroyed one day (in the pattern
isel also) since ia64 can pack any constant in the instruction stream

llvm-svn: 24094

llvm-svn: 24088

llvm-svn: 24080

llvm-svn: 24075

llvm-svn: 24073

tracked as PR642

llvm-svn: 24068

llvm-svn: 24067

llvm-svn: 24064

llvm-svn: 24063

use -enable-ia64-dag-isel to turn this on

TODO: delete lowering stuff from the pattern isel
    : get operations on predicate bits working
    : get other bits of pseudocode going
    : use sampo's mulh/mull-using divide-by-constant magic
    : *so* many patterns ("extr", "tbit" and "dep" will be fun :)
    : add FP
    : add a JIT!
    : get it working 100%

in short: this'll be happier in a couple of weeks, but it's here now so
the tester can make me feel guilty sooner.

OTHER: there are a couple of fixes to the pattern isel, in particular
making the linker happy with big blobs of fun like pypy.

llvm-svn: 24058

llvm-svn: 24054

llvm-svn: 24053

llvm-svn: 24051

llvm-svn: 24020

llvm-svn: 24018

llvm-svn: 24017

llvm-svn: 24016

llvm-svn: 24014

llvm-svn: 24013

llvm-svn: 24012

to make it easy to use them.  This lets you write patterns like:

(set PRRC:$rd, (setne GPRC:$rS, imm:$SH))

and stuff.

llvm-svn: 24009

llvm-svn: 23994

machine.  This allows us to generate great code for i32 FP_TO_UINT now on
targets with 64 bit extensions.

llvm-svn: 23993

llvm-svn: 23991

llvm-svn: 23990

llvm-svn: 23988

llvm-svn: 23987