missed in the first pass because the script didn't yet handle include
guards.

Note that the script is now able to handle all of these headers without
manual edits. =]

llvm-svn: 169224

Allow targets to access this API. It's required for RegisterPressure.

llvm-svn: 158102

llvm-svn: 152999

No functional change was intended.

llvm-svn: 133202

llvm-svn: 132487

llvm-svn: 125232

Avoid using the same register for two def operands or and earlyclobber
def and use operand. This fixes PR8986 and improves on the prior fix
for rdar://problem/8959122.

llvm-svn: 125089

breaker needs to check all definitions of the antidepenent register to
avoid multiple defs of the same new register.

llvm-svn: 118032

make sure to allocate enough space in the std::vector.

llvm-svn: 108449

llvm-svn: 108419

get *very* large, but we only need it to be the size of thenumber of pregs.

llvm-svn: 108411

Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler.

llvm-svn: 106091

and End arguments by-value rather than by-reference.

llvm-svn: 101830

multiple register definitions.

llvm-svn: 92864

llvm-svn: 92837

Remove some old experimental code that is no longer needed. Remove additional, speculative scheduling pass as its cost did not translate into significant performance improvement. Minor tweaks.

llvm-svn: 89471

Do a scheduling pass ignoring anti-dependencies to identify candidate registers that should be renamed.

llvm-svn: 85939

llvm-svn: 85412

Allow the aggressive anti-dep breaker to process the same region multiple times. This is necessary because new anti-dependencies are exposed when "current" ones are broken.

llvm-svn: 85166

llvm-svn: 85127