llvm-svn: 186907

This makes them consistent with 'bt' which already had this handling. gas has the same behavior. There have been discussions on the mailing list about determining size based on the immediate, but my goal here was just to remove the inconsistency.

llvm-svn: 186904

It only didn't use it before because it seems InstAlias handling in the asm printer fails to count tied operands so it tried to find an xor with 2 operands instead of the 3 it wfails to count tied.

llvm-svn: 186900

Suppress argumentless aliases for some x86 FP operations from being used by the asm writer. Prefer to use the explicit %st(1) form.

llvm-svn: 186897

absolute address encoded in the instruction.

rdar://8612627 and rdar://14299221

llvm-svn: 186878

Recommit r186813: More Intel syntax alias fixes. With the addition of suppressing some of the aliases from being emitted by the asm printer.

llvm-svn: 186869

Enable parsing all 32 floating point control registers $0-31 and stop trying to
parse floating point condition code register $fcc0. Also, return ParseFail if
the operand being parsed is not in the expected format. 

llvm-svn: 186861

the InstAlias pattern which maps "move" to OR to resolve ambiguity in
MatchTable.

llvm-svn: 186855

llvm-svn: 186844

instructions. With this patch:

1. ldr.n is recognized as mnemonic for the short encoding
2. ldr.w is recognized as menmonic for the long encoding
3. ldr will map to either short or long encodings depending on the size of the offset

llvm-svn: 186831

.ftz to instructions if the nvptx-f32ftz attribute is set to "true"

llvm-svn: 186820

This reverts commit r186813, which broke the bots.

llvm-svn: 186818

llvm-svn: 186815

llvm-svn: 186814

llvm-svn: 186813

llvm-svn: 186812

llvm-svn: 186811

After Ulrich's r180677 (thanks!) TableGen is intelligent enough to
handle tied constraints involving complex operands properly, so
virtually all of the ARM custom converters are now unnecessary.

llvm-svn: 186810

llvm-svn: 186809

deallocation functions.

llvm-svn: 186798

llvm-svn: 186787

indirect branches correctly. Under some circumstances, this led to the deletion
of basic blocks that were the destination of indirect branches. In that case it
left indirect branches to nowhere in the code.

This patch replaces, and is more general than either of the previous fixes for
indirect-branch-analysis issues, r181161 and r186461.

For other branches (not indirect) this refactor should have *almost* identical
behavior to the previous version. There are some corner cases where this
refactor is able to analyze blocks that the previous version could not (e.g.
this necessitated the update to thumb2-ifcvt2.ll). 

<rdar://problem/14464830>

llvm-svn: 186735

llvm-svn: 186725

llvm-svn: 186724

llvm-svn: 186723

llvm-svn: 186692

Follows the same lines as r186686, but much more limited, since we only
use ADD LOGICAL for multi-i64 additions.

llvm-svn: 186689

llvm-svn: 186688

I did these as a separate patch because it uses a slightly different
form of RIE layout.

llvm-svn: 186687

The testsuite changes follow the same lines as for r186683.

llvm-svn: 186686

Like r186683, but for 64 bits.

llvm-svn: 186685

The atomic tests assume the two-operand forms, so I've restricted them to z10.

Running and-01.ll, or-01.ll and xor-01.ll for z196 as well as z10 shows why
using convertToThreeAddress() is better than exposing the three-operand forms
first and then converting back to two operands where possible (which is what
I'd originally tried).  Using the three-operand form first stops us from
taking advantage of NG, OG and XG for spills.

llvm-svn: 186683

See A8.8.127 in ARM DDI 0406C.b.

Related to <rdar://problem/14403733>.

llvm-svn: 186682

This patch uses the instructions added in r186680 for codegen.

llvm-svn: 186681

This first step just adds definitions for SLLK, SRLK and SRAK.
The next patch will actually make use of them during codegen.

insn-bad.s tests that some form of error is reported when using these
instructions on z10.  More work is needed to get the "instruction requires:
distinct-ops" that we'd ideally like, so I've stubbed that part out for now.
I'll come back and make it mandatory once the necessary changes are in.

llvm-svn: 186680

No functionality change.

llvm-svn: 186642

PLI requires both the Thumb2 and the ARMv7 feature.

Related to <rdar://problem/14403733>.

llvm-svn: 186620

https://bugs.freedesktop.org/show_bug.cgi?id=66175

llvm-svn: 186616

llvm-svn: 186615

llvm-svn: 186614