* Add a lot more DEBUG output, which is better structured than before
* Fix bug: Jello/2003-08-04-PhysRegLiveFailure.llx

llvm-svn: 7583

llvm-svn: 7533

llvm-svn: 7503

llvm-svn: 7497

    Fixed spilling of %fcc[0-3] which are part of %fsr.

(2) Moved some machine-independent reg-class code to class TargetRegInfo
    from SparcReg{Class,}Info.

(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
    and related functions and flags.  Fixed several bugs where only
    "isDef" was being checked, not "isDefAndUse".

llvm-svn: 6341

llvm-svn: 6109

llvm-svn: 6002

llvm-svn: 5326

llvm-svn: 5272

* Convert to use PHIElimination pass
* Don't spill values which have just been reloaded (big win reducing spills)
* Add experimental support for eliminating spills before TwoAddress
  instructions.  It currently is broken so it is #ifdef'd out.
* Use new "is terminator" flag on instructions instead of looking for
  branches and returns explicitly.

llvm-svn: 5219

llvm-svn: 5200

* Use new FunctionFrameInfo object to manage stack slots instead of doing
  it directly
* Adjust to new MRegisterInfo API
* Don't take a TM as a ctor argument
* Don't keep track of which callee saved registers are modified
* Don't emit prolog/epilog code or spill/restore code for callee saved regs
* Use new allocation_order_begin/end iterators to simplify dramatically the
  logic for picking registers to allocate
* Machine PHI nodes can no longer contain constant arguments

llvm-svn: 5195

Only spill and reload caller saved registers that are actually modified.

llvm-svn: 5145

strtol to not miscompile, and fixing bug: 2002-12-23-LocalRAProblem.llx

llvm-svn: 5132

* Add a new option to eliminate spilling of registers that are only used
  within a basic block.

llvm-svn: 5106

llvm-svn: 5099

Move X86 specific alignment gunk to X86 files

llvm-svn: 5096

llvm-svn: 5093

* Implement register alias set support

llvm-svn: 5082

llvm-svn: 5078