llvm-svn: 74138

llvm-svn: 74097

a bunch of code from all the targets, and eliminates nondeterministic
ordering of directives being emitted in the output.

llvm-svn: 74096

llvm-svn: 74046

llvm-svn: 74042

createSCEV. Also, recognize UndefValue in createSCEV.

Change getIntegerSCEV's comment to avoid mentioning FP types,
and re-implement it in terms of getConstant instead of getUnknown.

llvm-svn: 74041

C bindings.  Change all the backend "Initialize" functions to have C linkage.
Change the "llvm/Config/Targets.def" header to use C-style comments to avoid
compile warnings.

llvm-svn: 74026

llvm-svn: 73990

llvm-svn: 73987

llvm-svn: 73986

Add IsThumb1Only to most 16-bit thumb instructions since we want to isel 32-bit instructions when they are available.

llvm-svn: 73985

llvm-svn: 73975

cleans up the CMake-based build system a bit. Started by a patch from
Xerxes Rånby.

llvm-svn: 73969

llvm-svn: 73967

also some contribution from Jim Grosbach, Bob Wilson, and Evan Cheng.

I've done my best to consolidate the patches with those that were done by
Viktor Kutuzov and Anton Korzh from Access Softek, Inc. Let me know if missed
anything. I've completely reorganized the thumb2 td file, made more extensive
uses of multiclass, etc.

Test cases will be contributed later after I re-organize what's in svn first.

llvm-svn: 73965

llvm-svn: 73948

llvm-svn: 73947

This is still a work in progress but most of the NEON instruction set
is supported.

llvm-svn: 73919

another change that makes the types ambiguous (at least as far as tablegen
is concerned).

llvm-svn: 73909

for "thumb" and add a check for V6T2.

llvm-svn: 73905

caller-saved register.

llvm-svn: 73901

llvm-svn: 73893

predicate does not check if Thumb mode is enabled, and when in ARM mode
there are still some checks for constant-pool use that need to run.

llvm-svn: 73887

llvm-svn: 73815

llvm-svn: 73791

llvm-svn: 73784

llvm-svn: 73761

llvm-svn: 73759

llvm-svn: 73749

Latency information for ARM v6. It's rough and not yet hooked up. Right now  we are only using branch latency to determine if-conversion limits.

llvm-svn: 73747

while experimenting.  I'm reasonably sure this is correct, but please 
tell me if these instructions have some strange property which makes this
change unsafe.

llvm-svn: 73746

into DarwinTargetAsmInfo.cpp.  The remaining differences should
be evaluated.  It seems strange that x86/arm has .zerofill but ppc
doesn't, etc.

llvm-svn: 73742

llvm-svn: 73738

llvm-svn: 73736

llvm-svn: 73734

On Darwin, ams printer should output a second label before a jump table so the linker knows it's a new atom. But this is only needed if the jump table is put in a separate section from the function body.

llvm-svn: 73720

- Update register allocation hint after coalescing. This is done by the target since the hint is target dependent. This is important for ARM register pair hints.
- Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping.
- More fixes to get ARM load / store double word working.

llvm-svn: 73671

llvm-svn: 73665

llvm-svn: 73661

Emit switch directive for it. I have no idea whether this is
requirement for Darwin or not.

llvm-svn: 73660