effect with the way the current code is structured.

llvm-svn: 79792

llvm-svn: 79763

llvm-svn: 79742

llvm-svn: 79731

llvm-svn: 79720

whitespace.

llvm-svn: 79711

llvm-svn: 79710

be of (dynamically) constant values, so races on it are immaterial.  We just need
to ensure that at least one write has completed before return the pointer into it.

With this change, parllc exhibits essentially no overhead on 403.gcc.

llvm-svn: 79708

llvm-svn: 79649

a smaller encoding. These kinds of patterns are very frequent in
sqlite3, for example.

llvm-svn: 79439

Use the schedule itinerary operand use/def cycle information to adjust dependence edge latency for post-RA scheduling.

llvm-svn: 79425

llvm-svn: 79415

just falling through the end.

llvm-svn: 79383

SRA_PARTS, as is done for SRL, SHL, and SRA.

llvm-svn: 79380

llvm-svn: 79272

If two uses of a CopyFromReg want different regclasses, first try a common
sub-class, then fall back on the copy emitted in AddRegisterOperand. There is
no need for an assert here. The cross-class joiner usually cleans up nicely.

llvm-svn: 79193

llvm-svn: 79150

llvm-svn: 79133

llvm-svn: 79087

llvm-svn: 79068

libcall. Take advantage of this in the ARM backend to rectify broken
choice of CC when hard float is in effect. PIC16 may want to see if
it could be of use in MakePIC16Libcall, which works unchanged.

Patch by Sandeep!

llvm-svn: 79033

llvm-svn: 78978

llvm-svn: 78948

llvm-svn: 78910

Add contexts to some of the MVT APIs.  No functionality change yet, just the infrastructure work needed to get the contexts to where they need to be first.

llvm-svn: 78759

llvm-svn: 78725

the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713

llvm-svn: 78677

and short. Well, it's kinda short. Definitely nasty and brutish.

The front-end generates the register/unregister calls into the SjLj runtime,
call-site indices and landing pad dispatch. The back end fills in the LSDA
with the call-site information provided by the front end. Catch blocks are
not yet implemented.

Built on Darwin and verified no llvm-core "make check" regressions.

llvm-svn: 78625

MERGE_VALUES nodes. Replacing the result values with the
operands in one MERGE_VALUES node may cause another
MERGE_VALUES node be CSE'd with the first one, and bring
its uses along, so that the first one isn't dead, as this
code expects. Fix this by iterating until the node is
really dead. This fixes PR4699.

llvm-svn: 78619

node after legalize, and remove the workaround code from the
ARM backend.

llvm-svn: 78615

llvm-svn: 78610

Start moving TargetLowering away from using full MVTs and towards SimpleValueType, which will simplify the privatization of IntegerType in the future.

llvm-svn: 78584

llvm-svn: 78569

Blackfin supports and/or/xor on i32 but not on i16. Teach
DAGCombiner::SimplifyBinOpWithSameOpcodeHands to not produce illegal nodes
after legalize ops.

llvm-svn: 78497

llvm-svn: 78350

and LowerReturn, to verify that the targets' hooks have respected some
of their postconditions.

llvm-svn: 78312

types don't have any return values, from CodeGen's perspective.
This fixes PR4688.

llvm-svn: 78311

and high-bits values in ways that weren't correct for integer
types wider than 64 bits. This fixes a miscompile in
PPMacroExpansion.cpp in clang on x86-64.

llvm-svn: 78295

Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.

This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.

This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.

llvm-svn: 78142