generation to always catch the weird cases.

llvm-svn: 136453

llvm-svn: 136451

Later passes /are/ using this information when running the register
scavenger.

This fixes the second problem in PR10520.

llvm-svn: 136440

This hidden llc option runs the machine code verifier after expanding
ARM pseudo-instructions, but before if-conversion.

The machine code verifier is much better at pointing out liveness errors
that can trip up the register scavenger.

llvm-svn: 136439

Make sure to correctly clear the exact/nuw/nsw flags off of shifts when they are combined together. <rdar://problem/9859829>

llvm-svn: 136435

llvm-svn: 136408

Add parsing support for BLX (immediate). Since the register operand version is
predicated and the label operand version is not, we have to use some special
handling to get the operand list right for matching.

llvm-svn: 136406

Code like that would only be produced by bugpoint, but we should still
handle it correctly.

When a register is defined by a REG_SEQUENCE of undefs, the register
itself is undef. Previously, we would create a register with uses but no
defs.

Fixes part of PR10520.

llvm-svn: 136401

llvm-svn: 136400

Add parsing support that handles converting the lsb+width source into the
odd way we represent the instruction (an inverted bitfield mask).

llvm-svn: 136399

The label does not have a '#' prefix. Add parsing and encoding tests.

llvm-svn: 136360

llvm-svn: 136358

bitcasts in this test rather than getelementptr instructions;
llvm-gcc produces two bitcasts, clang produces one.

llvm-svn: 136349

using vextractf128. This will reduce the number of issued instruction
for several avx codes.

llvm-svn: 136323

Take advantage that the 128-bit vpxor zeros the higher part and use it.
This also fixes PR10491

llvm-svn: 136321

a convert pattern close to the instruction definition.

llvm-svn: 136320

UXTAB, UXTAB16, UXTAH, UXTB, UXTB16, and UXTH.

llvm-svn: 136312

This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.

rdar://8204588

llvm-svn: 136292

llvm-svn: 136289

llvm-svn: 136288

llvm-mc gives an "invalid operand" error for instructions that take an unsigned
immediate which have the high bit set such as:
    pblendw $0xc5, %xmm2, %xmm1
llvm-mc treats all x86 immediates as signed values and range checks them.
A small number of x86 instructions use the imm8 field as a set of bits.
This change only changes those instructions and where the high bit is not
ignored.  The others remain unchanged.

llvm-svn: 136287

llvm-svn: 136286

Use range checked immediate operands for instructions. Add tests.

llvm-svn: 136285

llvm-svn: 136284

llvm-svn: 136282

llvm-svn: 136281

llvm-svn: 136280

llvm-svn: 136279

Fix parsing of the 's' suffix for the mnemonic. Add tests.

llvm-svn: 136277

Fix parsing of the 's' suffix for the mnemonic. Add tests.

llvm-svn: 136274

llvm-svn: 136272

llvm-svn: 136267

llvm-svn: 136266

Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].

llvm-svn: 136264

llvm-svn: 136261

llvm-svn: 136260

llvm-svn: 136259

Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions.  Temporarily XFAIL the asm parsing tests for these instructions.

llvm-svn: 136255

This adds the new instructions 'landingpad' and 'resume'.

llvm-svn: 136253

Assembly parser handling for extend instruction rotate operands. Add tests
for the sign extend instructions.

llvm-svn: 136252