For example, "mlss r0, r1, r2, r3".

The MLS instruction does not have a flag-setting variant.

llvm-svn: 135203

  unwind library expects.
* Comment the permutation encoding for frameless stacks.

llvm-svn: 135202

llvm-svn: 135199

llvm-svn: 135198

llvm-svn: 135192

The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.

llvm-svn: 135189

llvm-svn: 135186

registeration and creation code into XXXMCDesc libraries.

llvm-svn: 135184

when determining validity of matching constraint. Allow i1
types access to the GR8 reg class for x86.

Fixes PR10352 and rdar://9777108

llvm-svn: 135180

Consolidate the individual declarations together for ease of reference. This
mirrors the organization in X86, as well, so is good for consistency. No
functional change.

llvm-svn: 135179

llvm-svn: 135171

llvm-svn: 135169

ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.

llvm-svn: 135168

The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.

llvm-svn: 135156

instructions.

llvm-svn: 135146

[VECTOR-SELECT]
During type legalization we often use the SIGN_EXTEND_INREG SDNode.
When this SDNode is legalized during the LegalizeVector phase, it is
scalarized because non-simple types are automatically marked to be expanded.
In this patch we add support for lowering SIGN_EXTEND_INREG manually.
This fixes CodeGen/X86/vec_sext.ll when running with the '-promote-elements'
flag.

llvm-svn: 135144

TargetAsmInfo, which in turn pulls in TargetRegisterInfo, etc. :-( There are
other cases of violations, but this is probably the worst.

This patch is but one small step towards fixing this. 500 more steps to go. :-(

llvm-svn: 135131

Don't emit a bit test if there is only one case the test can yield false. A simple SETNE is sufficient.

llvm-svn: 135126

Fix up assertion in r135018 so it doesn't trigger on 32-bit; when we're in 32-bit, it doesn't matter whether the operation overflows because the computed address is not wider than the immediate.

llvm-svn: 135120

Add instalias for default 'sy' option. Add tests.

llvm-svn: 135116

llvm-svn: 135112

Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".

llvm-svn: 135109

llvm-svn: 135107

Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode.  Switch ARM over to using that rather than its own special MCInstrDesc bits.

llvm-svn: 135106

The frameless unwind stack has a special encoding, the algorithm for which is in
"permuteEncode".

llvm-svn: 135103

Add range checking and testing for parsing and encoding of DBG instruction.

llvm-svn: 135102

llvm-svn: 135094

llvm-svn: 135093

llvm-svn: 135092

general version of X86ISD::ANDNP also opened the room for a little bit
of refactoring.

llvm-svn: 135088

it's later selected to a ANDNPD/ANDNPS instruction instead of the PANDN
instruction. Rename it.

llvm-svn: 135087

Combine redundant base classes and such. No indended functional change.

llvm-svn: 135085

Make sure we don't combine a large displacement and a frame index in the same addressing mode on x86-64.  It can overflow, leading to a crash/miscompile.

<rdar://problem/9763308>

llvm-svn: 135084

llvm-svn: 135082

They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.

llvm-svn: 135081

Refactor out checking for displacements on x86-64 addressing modes.  No functionality change.  Refactoring in preparation for an additional safety check in FoldOffsetIntoAddress.

Part of <rdar://problem/9763308>.

llvm-svn: 135079

llvm-svn: 135077

llvm-svn: 135076

llvm-svn: 135071

llvm-svn: 135068