not just the first letter.  No functionality change.

llvm-svn: 35322

Allow the b/h/w/k constraints to be applied to values that have multiple alternatives, and end up not being registers.

llvm-svn: 35320

llvm-svn: 35319

llvm-svn: 35318

llvm-svn: 35292

Add final support to get the QT example to compile.

llvm-svn: 35290

intrinsic.

llvm-svn: 35269

llvm-svn: 35266

llvm-svn: 35245

llvm-svn: 35241

llvm-svn: 35230

llvm-svn: 35205

1) codegen a shift of a register as a shift, not an LEA.
2) teach the RA to convert a shift to an LEA instruction if it wants something
   in three-address form.

This gives us asm diffs like:

-       leal (,%eax,4), %eax
+       shll $2, %eax

which is faster on some processors and smaller on all of them.

and, more interestingly:

-       movl 24(%esi), %eax
-       leal (,%eax,4), %edi
+       movl 24(%esi), %edi
+       shll $2, %edi

Without #2, #1 was a significant pessimization in some cases.

This implements CodeGen/X86/shift-codegen.ll

llvm-svn: 35204

llvm-svn: 35152

llvm-svn: 35129

llvm-svn: 35125

llvm-svn: 35118

llvm-svn: 35108

llvm-svn: 35107

llvm-svn: 35105

llvm-svn: 35104

llvm-svn: 35097

llvm-svn: 35096

llvm-svn: 35095

 a legal target address immediate or scale.

llvm-svn: 35073

llvm-svn: 35070

the addition. Please let me know if you have suggestions.

llvm-svn: 35055

moves, loads, etc. are recognized.

llvm-svn: 35031

llvm-svn: 35026

llvm-svn: 35016

llvm-svn: 35009

zext/sext/aext stuff.

llvm-svn: 35008

load and stores.

llvm-svn: 35002

Mingw32/Cygwin targets. This fixes PR978

llvm-svn: 35000

llvm-svn: 34978

from formal attributes' flags processing.

llvm-svn: 34963

llvm-svn: 34938

llvm-svn: 34905

llvm-svn: 34857

llvm-svn: 34849