like normal integers.

llvm-svn: 149223

llvm-svn: 149222

when the result type has a different # elements than the input vectors.

llvm-svn: 149221

Move some XOP patterns into instruction definition. Replae VPCMOV intrinsic patterns with custom lowering to a target specific nodes.

llvm-svn: 149216

should be feature complete now.  Lets see if it works.

llvm-svn: 149215

library, since it doesn't really have anything to do with Clang.

llvm-svn: 149203

llvm-svn: 149195

llvm-svn: 149194

- Don't call malloc+free in the very hot forward().
- Don't call isTiedToDefOperand().
- Don't create BitVector temporaries.
- Merge DeadRegs into KillRegs.
- Eliminate the early clobber checks, they were irrelevant to scavenging.
- Remove unnecessary code from -Asserts builds.

This speeds up ARM PEI by 3.4x and overall llc -O0 codegen time by 11%.

llvm-svn: 149189

llvm-svn: 149188

llvm-svn: 149185

(and other targets).

llvm-svn: 149182

Fixes PR11877

llvm-svn: 149180

llvm-svn: 149179

llvm-svn: 149175

messages and allows us to fix PR11865.

llvm-svn: 149174

llvm-svn: 149172

llvm-svn: 149164

llvm-svn: 149163

llvm-svn: 149162

Sometimes there is only one 'resume' instruction per function. In those
situations, we don't need a separate block for the call to _Unwind_Resume. In
fact, it adds a lot of overhead to code-gen if we do that -- especially at -O0.
If we have a single 'resume' instruction, just generate the call within that
block.
<rdar://problem/10694814>

llvm-svn: 149159

Get the record name though the init to avoid an assert.

llvm-svn: 149153

llvm-svn: 149152

width.

llvm-svn: 149151

Unfortunately I also had to disable constant-pool-sharing.ll the code it tests has been
updated to use the IL logic.

llvm-svn: 149148

around within a basic block while maintaining live-intervals.

Updated ScheduleTopDownLive in MachineScheduler.cpp to use the moveInstr API
when reordering MIs.

llvm-svn: 149147

llvm-svn: 149146

llvm-svn: 149144

llvm-svn: 149142

Move some patterns back near their instructions and use AddedComplexity to fix priority. Merge some patterns into their instruction definition.

llvm-svn: 149122

llvm-svn: 149118

llvm-svn: 149117

we should (theoretically optimize and codegen ConstantDataVector as well
as ConstantVector.

llvm-svn: 149116

GEP instructions are there for the compiler and shouldn't really output much
code (if any at all). When a GEP is stored in the entry block, Fast ISel (for
one) will not know that it could fold it into further uses. For instance, inside
of the EH handling code. This results in a lot of unnecessary spills and loads
which bloat code and slows down pretty much everything.
<rdar://problem/10694814>

llvm-svn: 149114

llvm-svn: 149113

mid-level constant folding APIs instead of doing its own analysis.
This makes it more general (e.g. can now share a <2 x i64> with a
<4 x i32>) and avoid duplicating a bunch of logic.

llvm-svn: 149111

ConstantVector's to integer type.

llvm-svn: 149110

llvm-svn: 149106

llvm-svn: 149105

llvm-svn: 149102