llvm-svn: 97709

we sometimes emit nodes multiple times to string buffers to size them.
Compute the histogram correctly.

llvm-svn: 97708

Look ahead a bit to determine if a physical register def that is not marked dead is really alive. This is necessary to catch a lot of common cse opportunities for targets like x86.

llvm-svn: 97706

llvm-svn: 97705

sequence, just emit instruction predicates right before them.  This
exposes yet more factoring opportunitites, shrinking the X86 table 
to 79144 bytes.

llvm-svn: 97704

as the very last thing before node emission.  This should
dramatically reduce the number of times we do 'MatchAddress'
on X86, speeding up compile time.  This also improves comments
in the tables and shrinks the table a bit, now down to 
80506 bytes for x86.

llvm-svn: 97703

destroyed, it could leave stubs in the StubToResolverMap, which would confuse
the lookup for subsequent lazy compilations.

llvm-svn: 97698

numbers a ComplexPat will match into.

llvm-svn: 97696

a patch my Micah Villmow for PR6465.

llvm-svn: 97692

llvm-svn: 97691

llvm-svn: 97690

Fix a logic error. An instruction that has a live physical register def cannot be CSE'ed, but it *can* be used to replace a common subexpression.

llvm-svn: 97688

llvm-svn: 97687

llvm-svn: 97685

llvm-svn: 97684

llvm-svn: 97683

llvm-svn: 97682

Move MachineInstrExpressionTrait::getHashValue() out of line so it can skip over only virtual register defs. This matches what isEqual() is doing.

llvm-svn: 97680

Re-apply r97667 but with a little bit of thought put into the patch. This implements a special DenseMapInfo trait for DenseMap<MachineInstr*> that compare the value of the MachineInstr rather than the pointer value. Since the hashing and equality test functions ignore defs it's useful for doing CSE kind optimization.

llvm-svn: 97678

MULS <Rdm>, <Rn>, <Rdm>

according to A8.6.105 MUL Encoding T1.

llvm-svn: 97675

llvm-svn: 97673

llvm-svn: 97670

llvm-svn: 97667

CSE and recursive RAUW calls delete a node from the use list,
invalidating the use list iterator. There's currently no known
way to reproduce this in an unmodified LLVM, however there's no
fundamental reason why a SelectionDAG couldn't be formed which
would trigger this case.

llvm-svn: 97665

Machine CSE work in progress. It's doing some CSE now. But implicit def of physical registers are getting in the way.

llvm-svn: 97664

llvm-svn: 97663

and is too old to really care about the performance of the generated 
compiler.

llvm-svn: 97662

llvm-svn: 97661

Fix PR6444, note still doesn't compile libgcc2 all the way, but fixes that error.  May not fix it in an ABI complient way.  It wasn't clear what gcc does

llvm-svn: 97660

llvm-svn: 97659

--- Reverse-merging r97592 into '.':
U    lib/CodeGen/TargetLoweringObjectFileImpl.cpp

llvm-svn: 97657

and STRHT for disassembly only.

llvm-svn: 97655

Scope accelerator.

llvm-svn: 97652

entry we're about to process is obviously going to fail, don't
bother pushing a scope only to have it immediately be popped.
This avoids a lot of scope stack traffic in common cases.

Unfortunately, this requires duplicating some of the predicate
dispatch.  To avoid duplicating the actual logic I pulled each
predicate out to its own static function which gets used in
both places.

llvm-svn: 97651

SwitchOpcodeMatcher) and have DAGISelMatcherOpt form it.  This
speeds up selection, particularly for X86 which has lots of 
variants of instructions with only type differences.

llvm-svn: 97645

llvm-svn: 97644

of loops.

llvm-svn: 97642

llvm-svn: 97639

llvm-svn: 97635

better done by dag combine.

llvm-svn: 97633