Atomics.rst was not linked into the toctree.

Docs now build warning-free!

llvm-svn: 164356

yaml2obj.rst was not included in the toctree

Input from Michael Spencer.

llvm-svn: 164355

llvm-svn: 164354

llvm/test/CodeGen/ARM/fast-isel.ll: Fix possible typos, s/@unaligned_i16_store/@unaligned_i16_load/g.

I guess this had apparently passed in +Asserts possibly due to verborsity.

llvm-svn: 164350

Patch by Reed Kotler.

llvm-svn: 164349

llvm-svn: 164347

llvm-svn: 164346

non-halfword-aligned i16 loads/stores.
rdar://12304911

llvm-svn: 164345

llvm-svn: 164344

llvm-svn: 164343

The expression based expansion too often results in IR level optimizations
splitting the intermediate values into separate basic blocks, preventing
the formation of the VBSL instruction as the code author intended. In
particular, LICM would often hoist part of the computation out of a loop.

rdar://11011471

llvm-svn: 164340

A PHI can't create interference on its own. If two live ranges interfere
at a PHI, they must also interfere when leaving one of the PHI
predecessors.

llvm-svn: 164330

The old-fashioned many-to-one value mapping doesn't always work when
merging vector lanes. A value can map to multiple different values, and
it can even be necessary to insert new PHIs.

When a value number is defined by a copy from a value number that
required SSa update, include the live range of the copied value number
in the SSA update as well. It is not necessarily a copy of the original
value number any longer.

llvm-svn: 164329

llvm-svn: 164326

We already have HoistThenElseCodeToIf, this patch implements
SinkThenElseCodeToEnd. When END block has only two predecessors and each
predecessor terminates with unconditional branches, we compare instructions in
IF and ELSE blocks backwards and check whether we can sink the common
instructions down.

rdar://12191395

llvm-svn: 164325

llvm-svn: 164320

llvm-svn: 164317

llvm-svn: 164311

llvm-svn: 164309

llvm-svn: 164308

llvm-svn: 164307

llvm-svn: 164306

llvm-svn: 164305

llvm-svn: 164297

Patch from Amara Emerson.

llvm-svn: 164296

Change enum type in a static table to uint8_t instead. Saves about 700 hundred bytes of static data. Change unsigned char in same table to uint8_t for explicitness.

llvm-svn: 164285

llvm-svn: 164283

Toctree was not being interlinked properly.

llvm-svn: 164282

- Rewrite/merge pseudo-atomic instruction emitters to address the
  following issue:
  * Reduce one unnecessary load in spin-loop

    previously the spin-loop looks like

        thisMBB:
        newMBB:
          ld  t1 = [bitinstr.addr]
          op  t2 = t1, [bitinstr.val]
          not t3 = t2  (if Invert)
          mov EAX = t1
          lcs dest = [bitinstr.addr], t3  [EAX is implicit]
          bz  newMBB
          fallthrough -->nextMBB

    the 'ld' at the beginning of newMBB should be lift out of the loop
    as lcs (or CMPXCHG on x86) will load the current memory value into
    EAX. This loop is refined as:

        thisMBB:
          EAX = LOAD [MI.addr]
        mainMBB:
          t1 = OP [MI.val], EAX
          LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
          JNE mainMBB
        sinkMBB:

  * Remove immopc as, so far, all pseudo-atomic instructions has
    all-register form only, there is no immedidate operand.

  * Remove unnecessary attributes/modifiers in pseudo-atomic instruction
    td

  * Fix issues in PR13458

- Add comprehensive tests on atomic ops on various data types.
  NOTE: Some of them are turned off due to missing functionality.

- Revise tests due to the new spin-loop generated.

llvm-svn: 164281

LGTM by Michael Spencer

llvm-svn: 164280

Try not to violate conventions immediately before explaining them.

llvm-svn: 164278

llvm-svn: 164268

Make the TargetPrefix setting one big setting instead of being spread out
everywhere. No functional change.

llvm-svn: 164265

llvm-svn: 164264

llvm-svn: 164261

Soften the pattern-can-never-match error in TableGen into a warning. This pattern can be very useful in cases where you want to define a multiclass that covers both commutative and non-commutative operators (say, add and sub).

llvm-svn: 164256

Implement a correct copy constructor for Record.  Now that we're using the ID number as a key in maps (for determinism), it is imperative that ID numbers be globally unique, even when we copy construct a Record.
This fixes some obscure failure cases involving registers defined inside multiclasses or foreach constructs that would not receive a unique ID, and would end up being omitted from the AsmMatcher tables.

llvm-svn: 164251

A common coalescing conflict in vector code is lane insertion:

  %dst = FOO
  %src = BAR
  %dst:ssub0 = COPY %src

The live range of %src interferes with the ssub0 lane of %dst, but that
lane is never read after %src would have clobbered it. That makes it
safe to merge the live ranges and eliminate the COPY:

  %dst = FOO
  %dst:ssub0 = BAR

This patch teaches the new coalescer to resolve conflicts where dead
vector lanes would be clobbered, at least as long as the clobbered
vector lanes don't escape the basic block.

llvm-svn: 164250

This patch adds memory support functions which will later be used to implement section-specific protection handling in MCJIT.

llvm-svn: 164249

to improve compatibility with GNU as.

Based on a patch by PaX Team.

Fixed assertion failures on non-Darwin and added additional test cases.

llvm-svn: 164248