register-indirect address with an offset of 0.
It used to be that a DBG_VALUE is a register-indirect value if the offset
(operand 1) is nonzero. The new convention is that a DBG_VALUE is
register-indirect if the first operand is a register and the second
operand is an immediate. For plain registers use the combination reg, reg.

rdar://problem/13658587

llvm-svn: 180816

I'll fix the heuristic in a general way in a follow-up commit.

llvm-svn: 180815

No intended functionality changes.

llvm-svn: 180807

llvm-svn: 180806

llvm-svn: 180805

Patch by Zoran Jovanovic.

llvm-svn: 180804

Always fold a shuffle-of-shuffle into a single shuffle when there's only one
input vector in the first place. Continue to be more conservative when there's
multiple inputs.

rdar://13402653
PR15866

llvm-svn: 180802

llvm-svn: 180801

First, taking advantage of the fact that the virtual base registers are allocated in order of the local frame offsets, remove the quadratic register-searching behavior. Because of the ordering, we only need to check the last virtual base register created.

Second, store the frame index in the FrameRef structure, and get the frame index and the local offset from this structure at the top of the loop iteration. This allows us to de-nest the loops in insertFrameReferenceRegisters (and I think makes the code cleaner). I also moved the needsFrameBaseReg check into the first loop over instructions so that we don't bother pushing FrameRefs for instructions that don't want a virtual base register anyway.

Lastly, and this is the only functionality change, avoid the creation of single-use virtual base registers. These are currently not useful because, in general, they end up replacing what would be one r+r instruction with an add and a r+i instruction. Committing this removes the XFAIL in CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll

Jim has okayed this off-list.

llvm-svn: 180799

Patch by Oliver Pinter.

llvm-svn: 180797

This will make it easier to turn on struct-path aware TBAA since the metadata
format will change.

llvm-svn: 180796

llvm-svn: 180794

the inlined function has multiple returns.

rdar://problem/12415623

llvm-svn: 180793

The actual storage was already using unsigned, but the interface was using
uint64_t. This is wasteful on 32 bits and looks to be the root causes of
a miscompilation on Windows where a value was being sign extended to 64bits
to compare with the result of getSlotIndex.

Patch by Pasi Parviainen!

llvm-svn: 180791

llvm-svn: 180790

Texture cache is now used when shader type is not specified

llvm-svn: 180785

Differences in bitwidth between X and Y could exist even if C1 and C2 have
the same Log2 representation.

llvm-svn: 180779

s tightens up the encoding description for ARM post-indexed ldr instructions. All instructions in this class have bit 4 cleared. It turns out that there is a test case for this, but it was marked XFAIL.

llvm-svn: 180778

This fixes the optimization introduced in r179748 and reverted in r179750.

While the optimization was sound, it did not properly respect differences in
bit-width.

llvm-svn: 180777

llvm-svn: 180776

1. VarArgStyleRegisters: functionality that emits "store" instructions for byval regs moved out into separated method "StoreByValRegs". Before this patch VarArgStyleRegisters had confused use-cases. It was used for both variadic functions and for regular functions with byval parameters. In last case it created new stack-frame and registered it as VarArg frame, that is wrong.

This patch replaces VarArgsStyleRegisters usage for byval parameters with StoreByValRegs method.

2. In ARMMachineFunctionInfo, "get/setVarArgsRegSaveSize" was renamed to "get/setArgRegsSaveSize". By the same reason. Sometimes it was used for variadic functions, and sometimes for byval parameters in regular functions. Actually, this property means the size of registers, that keeps arguments, and thats why it was renamed.

3. In ARMISelLowering.cpp, ARMTargetLowering class, in methods computeRegArea and StoreByValRegs, VARegXXXXXX was renamed to ArgRegsXXXXXX still by the same reasons.

llvm-svn: 180774

This seemed like the cleanest way to find the test executable.  Also fix
the file mode.

llvm-svn: 180770

This fixes 2013-04-04-RelocAddend.ll. We don't have a testcase for non external
relocs with an Addend. I will try to write one.

llvm-svn: 180767

This will improve the performance of memory reads.

llvm-svn: 180762

llvm-svn: 180761

llvm-svn: 180760

llvm-svn: 180759

llvm-svn: 180758

llvm-svn: 180757

llvm-svn: 180756

v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache

llvm-svn: 180755

llvm-svn: 180754

llvm-svn: 180753

llvm-svn: 180752

llvm-svn: 180751

Revert the command line option patch. However, keep the part that makes this pass on Windows. I.e., we don't emit the target dependent attributes in a comment before the function.

llvm-svn: 180750

This will make it easier to turn on struct-path aware TBAA since the metadata
format will change.

llvm-svn: 180745

llvm-svn: 180744

This will make it easier to turn on struct-path aware TBAA since the metadata
format will change.

llvm-svn: 180743

- Revise previous patches of the same purpose by fixing
  *) grep <PA> | not grep <PB> semantically is not the same as
     CHECK: <PA>{{^<PB>.*$}} as the former will check all occurrences of <PA>
     while the later only check the first match. As the result, CHECK needs
     putting in all place where <PA> occurs.
  *) grep <PA> | count <N> needs a final CHECK-NOT of the same pattern.
     (As 'CHECK-<N>' is proposed for discussion, converting 'grep | count <N>'
      where N > 1 is postponed.)

llvm-svn: 180742