llvm-svn: 53535

disproving a condition.  This actually compiles the existing testcase
(udiv_select_to_select_shift) to:

define i64 @test(i64 %X, i1 %Cond) {
entry:
	%divisor1.t = lshr i64 %X, 3		; <i64> [#uses=1]
	%quotient2 = lshr i64 %X, 3		; <i64> [#uses=1]
	%sum = add i64 %divisor1.t, %quotient2		; <i64> [#uses=1]
	ret i64 %sum
}

instead of:

define i64 @test(i64 %X, i1 %Cond) {
entry:
	%quotient1.v = select i1 %Cond, i64 3, i64 4		; <i64> [#uses=1]
	%quotient1 = lshr i64 %X, %quotient1.v		; <i64> [#uses=1]
	%quotient2 = lshr i64 %X, 3		; <i64> [#uses=1]
	%sum = add i64 %quotient1, %quotient2		; <i64> [#uses=1]
	ret i64 %sum
}

llvm-svn: 53534

fixes PR2540.

llvm-svn: 53533

No functionality change.

llvm-svn: 53532

llvm-svn: 53531

No functionality change.

llvm-svn: 53530

llvm-svn: 53528

llvm-svn: 53527

conditionals and commenting the code better.

No functionality change.

llvm-svn: 53526

started complicating many loops ('for' loops, in fact).

llvm-svn: 53508

Remove dead code analyzing urem. 'urem' of power-of-2 is canonicalized to an
'and' instruction.

llvm-svn: 53506

llvm-svn: 53505

llvm-svn: 53504

Fix PR2536: a nasty spiller bug. If a two-address instruction uses a register but the use portion of its live range is not part of its liveinterval, it must be defined by an implicit_def. In that case, do not spill the use. e.g.
8   %reg1024<def> = IMPLICIT_DEF
12  %reg1024<def> = INSERT_SUBREG %reg1024<kill>, %reg1025, 2

The live range [12, 14) are not part of the r1024 live interval since it's defined by an implicit def. It will not conflicts with live interval of r1025. Now suppose both registers are spilled, you can easily see a situation where both registers are reloaded before the INSERT_SUBREG and both target registers that would overlap.

llvm-svn: 53503

llvm-svn: 53502

has exactly one MachineMemOperand, and change some X86 lowering code to
make use of it.

llvm-svn: 53498

llvm-svn: 53489

instead of using the frame index for the SVOffset, which was
inconsistent.

llvm-svn: 53486

llvm-svn: 53481

llvm-svn: 53480

use a timer group for the timers in SelectionDAGISel. Also,
Split scheduling out from emitting, to give each their own
timer.

llvm-svn: 53476

llvm-svn: 53474

llvm-svn: 53472

llvm-svn: 53471

llvm-svn: 53470

be no need to split the result of a vector RET node,
since they are always already legal.

llvm-svn: 53462

SINT_TO_FP libcall plus additional operations:
it might as well be a direct UINT_TO_FP libcall.
So only turn it into an SINT_TO_FP if the target
has special handling for SINT_TO_FP.

llvm-svn: 53461

llvm-svn: 53460

was presumably added after the rest of the code was
copied to LegalizeTypes.

llvm-svn: 53459

on 16 bit machines.

llvm-svn: 53458

llvm-svn: 53454

whitespace.

llvm-svn: 53453

llvm-svn: 53452

similar.

llvm-svn: 53451

llvm-svn: 53450

llvm-svn: 53449

llvm-svn: 53448

llvm-svn: 53447

the min/max values for an integer type, compare against the min/max
values we can prove contain the input.  This might be a tighter bound,
so this is general goodness.

llvm-svn: 53446

handle them in some code.

llvm-svn: 53445