llvm-svn: 35194

llvm-svn: 35190

Patch by Sheng Zhou.

llvm-svn: 35188

Patch by Zhou Sheng.

llvm-svn: 35187

llvm-svn: 35186

2. Replace uses of the "isPositive" utility function with APInt::isPositive

llvm-svn: 35185

Patch by Sheng Zhou.

llvm-svn: 35184

llvm-svn: 35169

implements Transforms/ScalarRepl/memset-aggregate-byte-leader.ll

llvm-svn: 35150

llvm-svn: 35146

Rearrange some code to simplify it now that shifts are binops

llvm-svn: 35145

Add some more micro-optimizations: x * 0 = 0, a - x = a --> x = 0.

llvm-svn: 35138

llvm-svn: 35137

Add new micro-optimizations.

Add icmp predicate snuggling. Given %x ULT 4, "icmp ugt %x, 2" becomes
"icmp eq %x, 3". This doesn't apply in any non-trivial cases yet due to missing
support for NE values in ValueRanges.

llvm-svn: 35119

llvm-svn: 35094

llvm-svn: 35093

llvm-svn: 35086

Fix PR1244 and Transforms/InstCombine/2007-03-13-CompareMerge.ll

llvm-svn: 35082

"APInt::getAllOnesValue(ShiftAmt).zextOrCopy(BitWidth)",
to handle ShiftAmt == BitWidth situation, use zextOrCopy() instead of
zext().

llvm-svn: 35080

  1. Ensure VTy, KnownOne and KnownZero have same bitwidth.
  2. Make code more efficient.

llvm-svn: 35078

llvm-svn: 35072

Patch by Zhou Sheng.

llvm-svn: 35064

Patch by Zhou Sheng.

llvm-svn: 35063

llvm-svn: 35062

  1. Replace getSignedMinValue() with getSignBit() for better code readability.
  2. Replace APIntOps::shl() with operator<<= for convenience.
  3. Make APInt construction more effective.

llvm-svn: 35060

optimization power.

llvm-svn: 35058

User from the list of I users.

llvm-svn: 35051

llvm-svn: 35027

llvm-svn: 35024

do the correctness/performance analysis testing.

llvm-svn: 35023

llvm-svn: 35022

Provide an APIntified version of MaskedValueIsZero. This will (temporarily)
cause a "defined but not used" message from the compiler. It will be used
in the next patch in this series.

Patch by Sheng Zhou.

llvm-svn: 35019

Add a new ComputeMaskedBits function that is APIntified. We'll slowly
convert things over to use this version. When its all done, we'll remove
the existing version.

llvm-svn: 35018

llvm-svn: 35003

llvm-svn: 35001

llvm-svn: 34996

llvm-svn: 34992

llvm-svn: 34984

llvm-svn: 34939

scalarrepl things down to elements, but mem2reg can't promote elements that
are memset/memcpy'd.  Until then, the code is disabled "0 &&".

llvm-svn: 34924