for fastcc from X86CallingConv.td.  This means that nested functions
are not supported for calling convention 'fastcc'.

llvm-svn: 42934

enabled by passing -tailcallopt to llc.  The optimization is
performed if the following conditions are satisfied:
* caller/callee are fastcc
* elf/pic is disabled OR
  elf/pic enabled + callee is in module + callee has
  visibility protected or hidden

llvm-svn: 42870

to its inverse.
Testing this as llcbeta

llvm-svn: 42661

llvm-svn: 42642

llvm-svn: 42640

llvm-svn: 42459

llvm-svn: 42413

Some assemblers do not recognize aliases pushfd, pushfq, popfd, and popfq. Just emit them as pushf and popf.

llvm-svn: 42371

llvm-svn: 42348

llvm-svn: 42335

Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after
all the kinks are worked out.

llvm-svn: 42285

llvm-svn: 42027

previously only done for 32-bit and smaller operands.

llvm-svn: 42024

llvm-svn: 41975

llvm-svn: 41962

llvm-svn: 41863

by flagging the associated instructions as being trivially rematerializable.

llvm-svn: 41775

llvm-svn: 41595

llvm-svn: 40702

mnemonics from their operands instead of single spaces. This makes the
assembly output a little more consistent with various other compilers
(f.e. GCC), and slightly easier to read. Also, update the regression
tests accordingly.

llvm-svn: 40648

Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load )

llvm-svn: 40628

Change the x86 backend to use extract_subreg for truncation operations. Passes DejaGnu, SingleSource and MultiSource.

llvm-svn: 40578

    __builtin_ia32_cvtss2si64
    __builtin_ia32_cvttss2si64
    __builtin_ia32_cvtsi642ss
    __builtin_ia32_cvtsd2si64
    __builtin_ia32_cvttsd2si64
    __builtin_ia32_cvtsi642sd

llvm-svn: 40411

llvm-svn: 40132

InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033

llvm-svn: 37625

llvm-svn: 37154

llvm-svn: 36494

llvm-svn: 32609

llvm-svn: 32587

llvm-svn: 32585

- Re-enable some codegen niceties for X86-64 static relocation model codegen.
- Clean ups, etc.

llvm-svn: 32238

immediate in small code model. The JIT cannot ensure GV's are placed in the
lower 4G.
- Some preliminary support for large code model.

llvm-svn: 32215

- Proper support for both small static and PIC modes under X86-64
- Some (non-optimal) support for medium modes.

llvm-svn: 32046

llvm-svn: 31952

Correct instructions for moving data between GR64 and SSE registers; also correct load i64 / store i64 from v2i64.

llvm-svn: 31795

llvm-svn: 31435

llvm-svn: 30891

llvm-svn: 30844

operand of a conditional branch to allow load folding into CMP / TEST
instructions.

llvm-svn: 30241