Patch by Sam Panzer!

llvm-svn: 160233

  - Make sure existence of "barrier".
  - Confirm reload corresponding to spill.

llvm-svn: 160232

llvm-svn: 160231

Allow the folding of vbroadcastRR to vbroadcastRM, where the memory operand is a spill slot.

PR12782.

Together with Michael Kuperstein <michael.m.kuperstein@intel.com>

llvm-svn: 160230

Add a micro-optimization to getNode of CONCAT_VECTORS when both operands are undefs.
Can't find a testcase for this because VECTOR_SHUFFLE already handles undef operands, but Duncan suggested that we add this.

Together with Michael Kuperstein <michael.m.kuperstein@intel.com>

llvm-svn: 160229

The notable fix is to look at any dependencies attached to the kill
instruction (or other instructions between MI nad the kill) where the
dependencies are specific to the register in question.

The old code implicitly handled this by rejecting the transform if *any*
other uses were found within the block, but after the start point. The
new code directly finds the kill, and has to re-use the existing
dependency scan to check for non-kill uses.

This was caught by self-host, but I found the bug via inspection and use
of absurd assert scaffolding to compute the kills in two ways and
compare them. So I have no useful testcase for this other than
"bootstrap". I'd work harder to reduce a test case if this particular
code were likely to live for a long time.

Thanks to Benjamin Kramer for reviewing the fix itself.

llvm-svn: 160228

struct __attribute__((visibility("hidden"))) zed {
};
struct __attribute__((visibility("hidden"))) zed;

Which is a bit silly and got a lot noisier now that we correctly handle
visibility pragmas. This patch fixes that and also has some extra quality
improvements:

* We now produce an error instead of a warning for

struct __attribute__((visibility("hidden"))) zed {
};
struct __attribute__((visibility("default"))) zed;

* The "after definition" warning now points to the new attribute that is
  ignored instead of pointing to the declaration.

llvm-svn: 160227

llvm-svn: 160226

Finishes rdar://11875995

llvm-svn: 160225

that we just copied from here and replace all uses.

Part of rdar://11875995

llvm-svn: 160224

APInt/APSInt classes.

Part of rdar://11875995

llvm-svn: 160223

AVX: Fix a bug in getTargetVShiftNode. The shift amount has to be a 128bit vector with the same element type as the input vector.
This is needed because of the patterns we have for the VP[SLL/SRA/SRL][W/D/Q] instructions.

llvm-svn: 160222

The unoptimized concat_vectors isd prevented the canonicalization of the vector_shuffle node.

llvm-svn: 160221

llvm-svn: 160220

No test case, there are no in-tree targets that require this.

llvm-svn: 160219

instead push the terminator for the branch down into the basic blocks of the subexpressions of '&&' and '||'
respectively.  This eliminates some artifical control-flow from the CFG and results in a more
compact CFG.

Note that this patch only alters the branches 'while', 'if' and 'for'.  This was complex enough for
one patch.  The remaining branches (e.g., do...while) can be handled in a separate patch, but they
weren't immediately tackled because they were less important.

It is possible that this patch introduces some subtle bugs, particularly w.r.t. to destructor placement.
I've tried to audit these changes, but it is also known that the destructor logic needs some refinement
in the area of '||' and '&&' regardless (i.e., their are known bugs).

llvm-svn: 160218

llvm-svn: 160217

llvm-svn: 160216

llvm-svn: 160215

a shared pointer to ease some memory management issues with a patch
I'm working on.

The main complication with using SPs for these objects is that most
methods that build up an UnwindPlan will construct a Row to a given
instruction point in a function, then add additional regsaves in
the next instruction point to that row and push it again.  A little
care is needed to not mutate the previous instruction point's Row
once these are switched to being held behing shared pointers.

llvm-svn: 160214

llvm-svn: 160212

Allow "frame variable" to find ivars without the need for "this->" or "self->".  

llvm-svn: 160211

llvm-svn: 160210

AVX).  Currently, if no aligned attribute is specified the alignment of a vector is
inferred from its size.  Thus, very large vectors will be over-aligned with no 
benefit.  Target owners should set this target max.

llvm-svn: 160209

Fixing a buildbot issue in GDBRemoteCommunicationServer due to an undefined constant in latest commit

llvm-svn: 160208

Catch uses of undefined physregs that haven't been added to basic block
live-in lists. Run the verifier to pinpoint the problem.

Also run the verifier when a virtual register use is not jointly
dominated by defs.

llvm-svn: 160207

uninitialized variable use, walk back over branches where we've reached all the
non-null successors, not just cases where we've reached all successors.

llvm-svn: 160206

All SCEV expressions used by LSR formulae must be safe to
expand. i.e. they may not contain UDiv unless we can prove nonzero
denominator.

Fixes PR11356: LSR hoists UDiv.

llvm-svn: 160205

This allows SCEVExpander to run on the IV expressions.

This codifies an assumption made by LSR to complete the fix for
PR11356, but I haven't been able to generate a separate unit test for
this part. I'm adding it as an extra safety check.

llvm-svn: 160204

llvm-svn: 160203

llvm-svn: 160202

intrinsics with target-indepdent intrinsics.  The first instruction(s) to be 
handled are the vector versions of count leading zeros (ctlz).

The changes here are to clang so that it generates a target independent 
vector ctlz when it sees an ARM dependent vector ctlz.  The changes in llvm 
are to match the target independent vector ctlz and in VMCore/AutoUpgrade.cpp 
to update any existing bc files containing ARM dependent vector ctlzs with 
target-independent ctlzs.  There are also changes to an existing test case in 
llvm for ARM vector count instructions and a new test for the bitcode upgrade.

<rdar://problem/11831778>

There is deliberately no test for the change to clang, as so far as I know, no
consensus has been reached regarding how to test neon instructions in clang;
q.v. <rdar://problem/8762292>

llvm-svn: 160201

intrinsics with target-indepdent intrinsics.  The first instruction(s) to be 
handled are the vector versions of count leading zeros (ctlz).

The changes here are to clang so that it generates a target independent 
vector ctlz when it sees an ARM dependent vector ctlz.  The changes in llvm 
are to match the target independent vector ctlz and in VMCore/AutoUpgrade.cpp 
to update any existing bc files containing ARM dependent vector ctlzs with 
target-independent ctlzs.  There are also changes to an existing test case in 
llvm for ARM vector count instructions and a new test for the bitcode upgrade.

<rdar://problem/11831778>

There is deliberately no test for the change to clang, as so far as I know, no
consensus has been reached regarding how to test neon instructions in clang;
q.v. <rdar://problem/8762292>

llvm-svn: 160200

<rdar://problem/11782789> Changes to the watchpoint implementation on ARM so that we single-step before stopping at the WP. This is necessary because on ARM the WP triggers before the opcode is actually executed, so we would be unable to continue since we would keep hitting the WP. We work around this by disabling the WP, single stepping and then putting the WP back in place.

llvm-svn: 160199

with one armv7 unwind.  I'll look at updating this or finding a
different way of fixing it later tonight.

llvm-svn: 160198

llvm-svn: 160197

kills.

This is causing miscompiles that I'm working on tracking down.

llvm-svn: 160196

current symbol context is a C++ or Objective-C
instance method.

Specifically, ensure that we fetch information
on the current block, not just the current
function.

llvm-svn: 160195

removes the largest scaling problem in the test cases from PR13225 when
ASan is switched to insert basic blocks in the natural CFG order.

It may also solve some scaling problems for more normal code with large
numbers of basic blocks and variables.

llvm-svn: 160194

multiple %diff's, only print the first tree and fallback to inline printing
for the rest of the diagnostic.

llvm-svn: 160193