and is already available, instead of falling back to emitting a load, fall
back to emitting a reg-reg copy.  This generates significantly better code
for some SSE testcases, as SSE has lots of two-address instructions and
none of them are read/modify/write.  As one example, this change does:

        pshufd %XMM5, XMMWORD PTR [%ESP + 84], 255
        xorps %XMM2, %XMM5
        cmpltps %XMM1, %XMM0
-       movaps XMMWORD PTR [%ESP + 52], %XMM0
-       movapd %XMM6, XMMWORD PTR [%ESP + 52]
+       movaps %XMM6, %XMM0
        cmpltps %XMM6, XMMWORD PTR [%ESP + 68]
        movapd XMMWORD PTR [%ESP + 52], %XMM6
        movaps %XMM6, %XMM0
        cmpltps %XMM6, XMMWORD PTR [%ESP + 36]
        cmpltps %XMM3, %XMM0
-       movaps XMMWORD PTR [%ESP + 20], %XMM0
-       movapd %XMM7, XMMWORD PTR [%ESP + 20]
+       movaps %XMM7, %XMM0
        cmpltps %XMM7, XMMWORD PTR [%ESP + 4]
        movapd XMMWORD PTR [%ESP + 20], %XMM7
        cmpltps %XMM4, %XMM0

... which is far better than a store followed by a load!

llvm-svn: 28001

llvm-svn: 27999

llvm-svn: 27998

Transforms/InstCombine/vec_insert_to_shuffle.ll

llvm-svn: 27997

for now.

Patch contributed by Alexander Friedman.

llvm-svn: 27994

llvm-svn: 27993

llvm-svn: 27992

(VAND, VADD, etc.). Legalizer will assert otherwise.

llvm-svn: 27991

llvm-svn: 27989

llvm-svn: 27988

PR748.

llvm-svn: 27987

- Fixed vararg support.

llvm-svn: 27985

nondeterminism being bad) could cause some trivial missed optimizations (dead
phi nodes being left around for later passes to clean up).

With this, llvm-gcc4 now bootstraps and correctly compares.  I don't know
why I never tried to do it before... :)

llvm-svn: 27984

recognize some simple affine IV's.

llvm-svn: 27982

llvm-svn: 27980

llvm-svn: 27975

llvm-svn: 27974

failres.

llvm-svn: 27973

llvm-svn: 27972

llvm-svn: 27971

llvm-svn: 27970

llvm-svn: 27968

llvm-svn: 27967

llvm-svn: 27966

result). Otherwise tblgen will pick the default (v16i8 for 128-bit vector).

llvm-svn: 27965

a temporary workaround for the 2-wide vector_shuffle problem (i.e. its mask
would have type v2i32 which is not legal).

llvm-svn: 27964

llvm-svn: 27963

llvm-svn: 27961

llvm-svn: 27960

llvm-svn: 27959

llvm-svn: 27958

llvm-svn: 27955

llvm-svn: 27954

llvm-svn: 27953

the jump table's range check block.  This re-enables 100% dense jump tables
by default on PPC & x86

llvm-svn: 27952

these.

llvm-svn: 27950

updating the machine CFG.

llvm-svn: 27949

llvm-svn: 27948

x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.

llvm-svn: 27947

Don't do all the lowering stuff for 2-wide build_vector's. Also, minor optimization for shuffle of undef.

llvm-svn: 27946