llvm-svn: 84943

llvm-svn: 84931

Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.

llvm-svn: 84911

llvm-svn: 84868

llvm-svn: 84849

Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly.

llvm-svn: 84843

Load / store multiple was missing opportunites when the load / store bundles are at the end of the bb. Test case is already in, the bug is exposed by subsequent commit.

llvm-svn: 84842

llvm-svn: 84832

llvm-svn: 84831

llvm-svn: 84826

llvm-svn: 84813

Yay for ASCII graphics!

llvm-svn: 84808

llvm-svn: 84798

for a few bugs.

llvm-svn: 84791

llvm-svn: 84785

llvm-svn: 84783

immediate operands when they will fit into the using instruction.

llvm-svn: 84778

llvm-svn: 84776

RMW preprocessing stuff was incorrect. Grab the stuff from x86 backend and disable some tests until it will be clever enough to handle them.

llvm-svn: 84775

llvm-svn: 84774

llvm-svn: 84773

Patch by Johnny Chen.

llvm-svn: 84767

llvm-svn: 84766

llvm-svn: 84764

variables. This pass can be invoked by llvm-ld or opt to traverse over the call graph 
to detect what function frames and their automatic variables can be overlaid.
Currently this builds an archive , but needs to be changed to a loadable module.

llvm-svn: 84753

llvm-svn: 84751

llvm-svn: 84738

Thanks to Johnny Chen for discovering the problem.

llvm-svn: 84732

a default value of zero.  This is important for decoding the instructions.
Patch by Johnny Chen, with some changes from me, too.

llvm-svn: 84730

llvm-svn: 84725

llvm-svn: 84713

llvm-svn: 84712

llvm-svn: 84711

llvm-svn: 84710

llvm-svn: 84709

llvm-svn: 84708

llvm-svn: 84707

llvm-svn: 84706

llvm-svn: 84704

llvm-svn: 84703