llvm-svn: 96410

into a roundss intrinsic, producing a cyclic dag.  The root cause
of this is badness handling ComplexPattern nodes in the old dagisel
that I noticed through inspection.  Eliminate a copy of the of the
code that handled ComplexPatterns by making EmitChildMatchCode call
into EmitMatchCode.

llvm-svn: 96408

build failures due to my fix for pr6111.

llvm-svn: 96402

llvm-svn: 96401

llvm-svn: 96399

llvm-svn: 96395

llvm-svn: 96393

If there exists a use of a build_vector that's the bitwise complement of the mask,
then transform the node to
(and (xor x, (build_vector -1,-1,-1,-1)), (build_vector ~c1,~c2,~c3,~c4)).

Since this transformation is only useful when 1) the given build_vector will
become a load from constpool, and 2) (and (xor x -1), y) matches to a single
instruction, I decided this is appropriate as a x86 specific transformation.
rdar://7323335

llvm-svn: 96389

llvm-svn: 96388

llvm-svn: 96387

Add support for emitting non-temporal stores for DAGs marked
non-temporal.  Fix from r96241 for botched encoding of MOVNTDQ.

Add documentation for !nontemporal metadata.

Add a simpler movnt testcase.

llvm-svn: 96386

to have the predicate on the pattern itself instead. Support for the new
ISel. Remove definitions of CarryDefIsUnused and CarryDefIsUsed since they are
no longer used anywhere.

llvm-svn: 96384

llvm-svn: 96383

llvm-svn: 96382

They won't work with the new ISel mechanism, as Requires predicates are no
longer allowed to reference the node being selected. Moving the predicate to
the patterns instead solves the problem.

This patch handles ARM mode. Thumb2 will follow.

llvm-svn: 96381

o Store Return State (SRSW, SRS)
o Load/Store Coprocessor (LDC/STC and friends)
o MSR (immediate)

llvm-svn: 96380

llvm-svn: 96378

terminator's list of successors.

llvm-svn: 96377

llvm-svn: 96372

llvm-svn: 96370

branch in ARM v4 code, since it gets clobbered by the return address before
it is used.  Instead of adding a new register class containing all the GPRs
except LR, just use the existing tGPR class.

llvm-svn: 96360

methods to try to have the type predicates be more logically positioned.

llvm-svn: 96349

and T->isPointerTy().  Convert most instances of the first form to the second form.
Requested by Chris.

llvm-svn: 96344

llvm-svn: 96343

llvm-svn: 96337

not the end of the field, fixing rdar://7651978

llvm-svn: 96330

Currently, whether a function is ISR or not is encoded in the section attribute for that function.

llvm-svn: 96322

elimination.  Before a DBG_VALUE could affect codegen.
The solution here is imperfect and not final.

llvm-svn: 96318

llvm-gcc but has been replaced with pad argument which don't need any
special backend support.

llvm-svn: 96312

as it also peeks at which registers are being used by other uses. This
makes LSR less sensitive to use-list order.

llvm-svn: 96308

at older buildbot messages, I see the failure predates
this patch.

llvm-svn: 96307

finished.

llvm-svn: 96304

but it's harder to believe it's the other candidate,
so reverting.  Temporarily I hope.

llvm-svn: 96303

strict about the requirements.

llvm-svn: 96301

We could almost use a multiclass for the signed/unsigned instructions, but
there are only 6 of them so I guess it's not worth it.

llvm-svn: 96297

llvm-svn: 96295

llvm-svn: 96294

llvm-svn: 96292

llvm-svn: 96290

llvm-svn: 96289