llvm-svn: 148550

Found by the clang static analyzer.

llvm-svn: 148543

Found by the clang static analyzer.

llvm-svn: 148541

Found by the clang static analyzer.

llvm-svn: 148540

warnings from gcc.

llvm-svn: 148539

Improve 256-bit shuffle splitting to allow 2 sources in each 128-bit lane. As long as only a single lane of the source is used in the lane in the destination. This makes the splitting match much closer to what happens with 256-bit shuffles when AVX is disabled and only 128-bit XMM is allowed.

llvm-svn: 148537

can't handle. Also don't produce non-zero results for things which won't be
transformed by SROA at all just because we saw the loads/stores before we saw
the use of the address.

llvm-svn: 148536

LSR has gradually been improved to more aggressively reuse existing code, particularly existing phi cycles. This exposed problems with the SCEVExpander's sloppy treatment of its insertion point. I applied some rigor to the insertion point problem that will hopefully avoid an endless bug cycle in this area. Changes:

- Always used properlyDominates to check safe code hoisting.

- The insertion point provided to SCEV is now considered a lower bound. This is usually a block terminator or the use itself. Under no cirumstance may SCEVExpander insert below this point.

- LSR is reponsible for finding a "canonical" insertion point across expansion of different expressions.

- Robust logic to determine whether IV increments are in "expanded" form and/or can be safely hoisted above some insertion point.

Fixes PR11783: SCEVExpander assert.

llvm-svn: 148535

llvm-svn: 148532

Release+Asserts build with -DBUILD_SHARED_LIBS=ON, the install
directory goes from 72MB to 70MB.

llvm-svn: 148530

Remove a low-quality test which was failing on Windows; test/CodeGen/X86/sret.ll is a better test for the relevant behavior.

llvm-svn: 148526

'insertvalue' instructions that recreate the structure returned by the
'landingpad' instruction. Because the 'insertvalue' instruction isn't supported
by FastISel, this can save a bit of time during -O0 compilation.

llvm-svn: 148520

llvm-svn: 148513

llvm-svn: 148497

llvm-svn: 148495

llvm-svn: 148493

Add a new form of MCOperand, for representing sub-instructions.  This is intended for supporting bundles through the MC layer, rather than lowering them pre-MC as we currently do for Thumb2 IT blocks.  Since these sub-instruction operands hold pointers to the sub-instructions, it is the responsibility of the target's AsmPrinter to provide storage for them for the duration of the EmitInstruction() call.

llvm-svn: 148492

rdar://10531041.

llvm-svn: 148490

llvm-svn: 148489

llvm-svn: 148487

llvm-svn: 148486

llvm-svn: 148485

llvm-svn: 148473

llvm-svn: 148467

llvm-svn: 148466

llvm-svn: 148465

llvm-svn: 148464

T's that are consequtively in memory.

llvm-svn: 148463

llvm-svn: 148462

llvm-svn: 148459

llvm-svn: 148456

llvm-svn: 148455

llvm-svn: 148454

Added methods to get the live range immediately before a given slot. Intended to parallel the getVNInfoBefore method.

llvm-svn: 148453

llvm-svn: 148451

  to instruction right after the last instruction in the bundle.
- Add a finalizeBundle() variant that doesn't specify LastMI. Instead, the code
  will find the last instruction in the bundle by following the 'InsideBundle'
  marker. This is useful in case bundles are formed early (i.e. during MI
  scheduling) but finalized later (i.e. after register allocator has finished
  rewriting virtual registers with physical registers).

llvm-svn: 148444

llvm-svn: 148442

llvm-svn: 148440

It adds register mask operands to x86 call instructions.  Once all the
backend passes support register mask operands, this will be permanently
enabled.

llvm-svn: 148438

This is similar to implicit register operands.  MC doesn't understand
register liveness and call clobbers.

llvm-svn: 148437