Add a test case to show fewer instructions are needed to load an immediate
with the new way of loading immediates.

llvm-svn: 148908

llvm-svn: 147676

nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU
nodes.

llvm-svn: 147008

llvm-svn: 147007

MIPS64 can generate constant +0.0 with a single DMTC1 instruction. 

llvm-svn: 146999

llvm-svn: 146996

llvm-svn: 146995

llvm-svn: 146896

This change reduces the number of instructions generated.

For example, 
(load (add (sub $n0, $n1), (MipsLo got(s))))

results in the following sequence of instructions:
1. sub $n2, $n0, $n1
2. lw got(s)($n2)

Previously, three instructions were needed.
1. sub $n2, $n0, $n1
2. addiu $n3, $n2, got(s)
3. lw 0($n3)

llvm-svn: 146888

llvm-svn: 146232

- Modify lowering of global TLS address nodes.
- Modify isel of ThreadPointer.
- Wrap target global TLS address nodes that are operands of loads with WrapperPIC. 
- Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be
  substituted with other existing nodes.

llvm-svn: 146175

llvm-svn: 146063

llvm-svn: 146062

llvm-svn: 146059

llvm-svn: 141615

llvm-svn: 141017

llvm-svn: 140214

Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This 
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.

Without the changes made in this patch, llc produces code that has the same 
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.

llvm-svn: 137711

integer register to a floating point register. It is not valid to interpret
the value of a floating pointer register as part of a double precision
floating point value after a single precision floating point computational
or move instruction stores its result to the register.

- In the test case, the following code is generated before this patch is
  applied:
mtc1  $zero, $f2    ; unformatted copy to $f2
mov.s $f0, $f2      ; $f0 is in single format
sdc1  $f12, 0($sp)
mov.s $f1, $f2      ; $f1 is in single format
c.eq.d  $f12, $f0   ; $f0 cannot be interpreted as double

- The following code is generated after this patch is applied:
mtc1  $zero, $f0    ; unformatted copy to $f0
mtc1  $zero, $f1    ; unformatted copy to $f1
c.eq.d  $f12, $f0   ; $f0 can be interpreted as double

Bhanu Chetlapalli and Chris Dearman at MIPS technologies reported this bug and
provided the test case.

llvm-svn: 137484

before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.

llvm-svn: 134625

static variables or functions. 

llvm-svn: 133803

llvm-svn: 133494

llvm-svn: 132777

llvm-svn: 132768

llvm-svn: 132725

- Fix indentation.
- Move comments.
- Fit lines in 80 columns.
- Remove dead code.

llvm-svn: 132724

llvm-svn: 132448

Dynamic, Initial Exec and Local Exec TLS models.

Patch by Sasa Stankovic

llvm-svn: 132322

Need this to prevent emitting illegal conditional move instructions. 

llvm-svn: 132240

llvm-svn: 129612

Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.

llvm-svn: 129606

Move transformation of JmpLink and related nodes done during instruction selection to Legalize phase.

llvm-svn: 128830

llvm-svn: 128751

llvm-svn: 128750

Remove redundant code. There are assignments to variables Base and Offset right after the code that is removed.

llvm-svn: 128742

llvm-svn: 127034

llvm-svn: 127027

llvm-svn: 127003

new gcc warning that complains on self-assignments and
self-initializations.

llvm-svn: 122458

something that just glues two nodes together, even if it is
sometimes used for flags.

llvm-svn: 122310