Fixing an issue where Unicode characters in an NSString were printed as escape sequences by the summary provider shipping with LLDB - Added relevant test case code. Bonus points for identifying the source of the quotes :-)

llvm-svn: 153624

llvm-svn: 153623

diagnostic and a fix-it to explain to the user where the ellipsis is
supposed to go.

llvm-svn: 153622

in the interface, got its attribute rewritten twice, resulting in
'weakweak' or 'strongstrong'.

rdar://11047179

llvm-svn: 153621

llvm-svn: 153620

llvm-svn: 153619

llvm-svn: 153618

This is a code change to add support for changing instruction sequences of the form:

  load
  inc/dec of 8/16/32/64 bits
  store

into the appropriate X86 inc/dec through memory instruction:

  inc[qlwb] / dec[qlwb]

The checks that were in X86DAGToDAGISel::Select(SDNode *Node)>>ISD::STORE have been extracted to isLoadIncOrDecStore and reworked to use the better
named wrappers for getOperand(unsigned) (e.g. getOffset()) and replaced Chain.getNode() with LoadNode.  The comments have also been expanded.

llvm-svn: 153617

Add a test for this too.

llvm-svn: 153616

Some targets still mess up the liveness information, but that isn't
verified after MRI->invalidateLiveness().

The verifier can still check other useful things like register classes
and CFG, so it should be enabled after all passes.

llvm-svn: 153615

The late scheduler depends on accurate liveness information if it is
breaking anti-dependencies, so we should be able to verify it.

Relax the terminator checking in the machine code verifier so it can
handle the basic blocks created by if conversion.

llvm-svn: 153614

a complete object, the memcpy needs to use the data size of
the structure instead of its sizeof() value.  Fixes PR12204.

llvm-svn: 153613

llvm-svn: 153612

When an strd instruction doesn't get the registers it wants, it can be
expanded into two str instructions. Make sure the first str doesn't kill
the base register in the case where the base and data registers are
identical:

  t2STRi12 %R0<kill>, %R0, 4, pred:14, pred:%noreg
  t2STRi12 %R2<kill>, %R0, 8, pred:14, pred:%noreg

<rdar://problem/11101911>

llvm-svn: 153611

When a number of sub-register VLRDS instructions are combined into a
VLDM, preserve any super-register implicit defs. This is required to
keep the register scavenger and machine code verifier happy.

Enable machine code verification after ARMLoadStoreOptimizer.
ARM/2012-01-26-CopyPropKills.ll was failing because of this.

llvm-svn: 153610

llvm-svn: 153609

Fixing an issue where saying 'po foo' made both the summary and the description for foo come out. If one is po'ing something they most probably only care about the description - We will not omit the summary

llvm-svn: 153608

llvm-svn: 153607

llvm-svn: 153604

The arm_neon intrinsics can create virtual registers from the DPair
register class which allows both even-odd and odd-even D-register pairs.

This fixes PR12389.

llvm-svn: 153603

llvm-svn: 153602

llvm-svn: 153601

llvm-svn: 153599

llvm-svn: 153598

Branch folding invalidates liveness and disables liveness verification
on some targets.

llvm-svn: 153597

Extract the liveness verification into its own method.

This makes it possible to run the machine code verifier after liveness
information is no longer required to be valid.

llvm-svn: 153596

a bunch of comments for the various functions. No intended functionality change.

llvm-svn: 153595

llvm-svn: 153594

Revert r153519: "ARMLoadStoreOptimizer invalidates register liveness."

These patches caused miscompilations in povray by turning off branch
folding's updating of live-in lists.

It turns out the the late scheduler depends on the live-in lists, even
if it doesn't need correct kill flags.

<rdar://problem/11139228>

llvm-svn: 153593

This avoids the silly double search:

  if (isLiveIn(Reg))
    removeLiveIn(Reg);

llvm-svn: 153592

llvm-svn: 153591

Also fix some Platform.h includes that somehow got missed last time.

llvm-svn: 153590

library depends on Core. This breaks that cycle.

llvm-svn: 153589

llvm-svn: 153588

Original commit message for r153521 (aka r153423):
Use the new range metadata in computeMaskedBits and add a new optimization to
instruction simplify that lets us remove an and when loding a boolean value.

llvm-svn: 153587

llvm-svn: 153586

Patch by Dmitri Shubin!

llvm-svn: 153585

provide 'fixit' hint when dictionary index 
is not of proper type. // rdar://11062080

llvm-svn: 153584

Converted commented out printf statements for dynamic type logging to use the log for "log enabe lldb types".

llvm-svn: 153583

llvm-svn: 153582