Commits · 870c4e92b90f30e8ac85e705936bbff4481d8d6b · Roger Ferrer / llvm-epi-0.8

Jan 11, 2012
- Add the skeleton of an asm parser for mips. · 870c4e92
  Rafael Espindola authored Jan 11, 2012
```
llvm-svn: 147923
```
  870c4e92
Jan 07, 2012
- Remove VectorExtras. This unused helper was written for a type of API that is discouraged now. · 6898db62
  Benjamin Kramer authored Jan 07, 2012
```
llvm-svn: 147738
```
  6898db62
Jan 06, 2012
- Fix uninitialized variable warning. · a3d90a94
  Chad Rosier authored Jan 06, 2012
```
llvm-svn: 147676
```
  a3d90a94
Jan 04, 2012
- Enable -soft-float for MIPS. · aac3e06b
  Akira Hatanaka authored Jan 04, 2012
```
llvm-svn: 147541
```
  aac3e06b
- Rename immLUiOpnd. · 3b775b8c
  Akira Hatanaka authored Jan 04, 2012
```
llvm-svn: 147519
```
  3b775b8c
- - Define base classes for Jump-and-link instructions and make 32-bit and 64-bit · b89a4bfe
  Akira Hatanaka authored Jan 04, 2012
```
  versions derive from them.
- JALR64 is not needed since N64 does not emit jal. 
- Add template parameter to BranchLink that sets the rt field. 
- Fix the set of temporary registers for O32 and N64.

llvm-svn: 147518
```
  b89a4bfe
- Have getRegForInlineAsmConstraint return the correct register class when target · c669d7a6
  Akira Hatanaka authored Jan 04, 2012
```
is Mips64.

llvm-svn: 147516
```
  c669d7a6
Dec 30, 2011

Cleanup Mips code and rename some variables. Patch by Jack Carter · cd1d447d
Bruno Cardoso Lopes authored Dec 30, 2011
```
llvm-svn: 147383
```
cd1d447d

Bruno Cardoso Lopes authored Dec 30, 2011

Implement encoder methods getJumpTargetOpValue and getBranchTargetOpValue
for jmptarget and brtarget Mips tablegen operand types in the code emitter
for old-style JIT. Rename the pc relative relocation for branches - new
name is Mips::reloc_mips_pc16.

Patch by Sasa Stankovic

llvm-svn: 147382

d5b2834f

Dec 24, 2011
- Add MachineMemOperands to instructions generated in storeRegToStackSlot or · 1cf75767
  Akira Hatanaka authored Dec 24, 2011
```
loadRegFromStackSlot. 

llvm-svn: 147235
```
  1cf75767
- Detect unaligned loads/stores that have been added for Mips64 support. · 6f54a461
  Akira Hatanaka authored Dec 24, 2011
```
llvm-svn: 147234
```
  6f54a461
- If target ABI is N64, LEA should be daddiu. · 695d113a
  Akira Hatanaka authored Dec 24, 2011
```
llvm-svn: 147232
```
  695d113a
Dec 22, 2011
- Move the Mips only bits of the ELF writer to lib/Target/Mips. · 1dc45d8d
  Rafael Espindola authored Dec 22, 2011
```
llvm-svn: 147133
```
  1dc45d8d
- Local dynamic TLS model for direct object output. Create the correct TLS MIPS · e2eed964
  Akira Hatanaka authored Dec 22, 2011
```
ELF relocations.

Patch by Jack Carter.

llvm-svn: 147118
```
  e2eed964
Dec 21, 2011
- Reduce the exposure of Triple::OSType in the ELF object writer. This will · 1ad4095d
  Rafael Espindola authored Dec 21, 2011
```
avoid including ADT/Triple.h in many places when the target specific bits are
moved.

llvm-svn: 147059
```
  1ad4095d
- Fix bug in zero-store peephole pattern reported in pr11615. · 964c891e
  Akira Hatanaka authored Dec 21, 2011
```
The patch and test case were originally written by Mans Rullgard.

llvm-svn: 147024
```
  964c891e
- Expand 64-bit CTLZ nodes if target architecture does not support it. Add test · 1d8efaba
  Akira Hatanaka authored Dec 21, 2011
```
case for DCLO and DCLZ.

llvm-svn: 147022
```
  1d8efaba
- Expand 64-bit CTPOP and CTTZ. · 410ce9cb
  Akira Hatanaka authored Dec 21, 2011
```
llvm-svn: 147021
```
  410ce9cb
- Expand 64-bit atomic load and store. · 91c052c4
  Akira Hatanaka authored Dec 21, 2011
```
llvm-svn: 147019
```
  91c052c4
- Add definition of DSBH (Double Swap Bytes within Halfwords) and · 4706ac97
  Akira Hatanaka authored Dec 20, 2011
```
DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.

llvm-svn: 147017
```
  4706ac97
- Add definition of WSBH (Word Swap Bytes within Halfwords), which is an · 43c1ff4d
  Akira Hatanaka authored Dec 20, 2011
```
instruction supported by mips32r2, and add a pattern which replaces bswap with
a ROTR and WSBH pair.
 
WSBW is removed since it is not an instruction the current architectures
support.

llvm-svn: 147015
```
  43c1ff4d
- 64-bit uint-fp conversion nodes are expanded. · 79aed157
  Akira Hatanaka authored Dec 20, 2011
```
llvm-svn: 147014
```
  79aed157
- Enable custom lowering DYNAMIC_STACKALLOC nodes. · 2bb8d068
  Akira Hatanaka authored Dec 20, 2011
```
llvm-svn: 147013
```
  2bb8d068
- Set the correct stack pointer register that should be saved or restored. · 8e2c02e2
  Akira Hatanaka authored Dec 20, 2011
```
llvm-svn: 147012
```
  8e2c02e2
- Add function MipsDAGToDAGISel::SelectMULT and factor out code that generates · cb2a85bc
  Akira Hatanaka authored Dec 20, 2011
```
nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU
nodes.

llvm-svn: 147008
```
  cb2a85bc
Dec 20, 2011
- Fix indentation. · 2c8d1734
  Akira Hatanaka authored Dec 20, 2011
```
llvm-svn: 147007
```
  2c8d1734
- 64-bit data directive. · cf10f088
  Akira Hatanaka authored Dec 20, 2011
```
llvm-svn: 147005
```
  cf10f088
- 32-to-64-bit sext_inreg pattern. · 494fdf14
  Akira Hatanaka authored Dec 20, 2011
```
llvm-svn: 147004
```
  494fdf14
- Add 64-bit extload patterns. · 8756816e
  Akira Hatanaka authored Dec 20, 2011
```
llvm-svn: 147003
```
  8756816e
- Add patterns for matching extloads with 64-bit address. The patterns are enabled · 0cee2045
  Akira Hatanaka authored Dec 20, 2011
```
only when the target ABI is N64.

llvm-svn: 147001
```
  0cee2045
- Add code in MipsDAGToDAGISel for selecting constant +0.0. · dac1d48d
  Akira Hatanaka authored Dec 20, 2011
```
MIPS64 can generate constant +0.0 with a single DMTC1 instruction. 

llvm-svn: 146999
```
  dac1d48d
- Revert part of r146995 that was accidentally commmitted. · 14468c6c
  Akira Hatanaka authored Dec 20, 2011
```
llvm-svn: 146996
```
  14468c6c
- 32-to-64-bit sign extension pattern. · 4e210691
  Akira Hatanaka authored Dec 20, 2011
```
llvm-svn: 146995
```
  4e210691
- Add a pattern for matching zero-store with 64-bit address. The pattern is enabled · 9b9bd1cc
  Akira Hatanaka authored Dec 20, 2011
```
only when the target ABI is N64. 

llvm-svn: 146992
```
  9b9bd1cc
- Fix up the CMake build for the new files added in r146960, they're · e805b16e
  Chandler Carruth authored Dec 20, 2011
```
likely to stay either way that discussion ends up resolving itself.

llvm-svn: 146966
```
  e805b16e
- Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch · a379b181
  David Blaikie authored Dec 20, 2011
```
llvm-svn: 146960
```
  a379b181
Dec 19, 2011
- Add patterns for matching immediates whose lower 16-bit is cleared. These · db47e0c4
  Akira Hatanaka authored Dec 19, 2011
```
patterns emit a single LUi instruction instead of a pair of LUi and ORi.

llvm-svn: 146900
```
  db47e0c4
- Tidy up. Simplify logic. No functional change intended. · 9e1d369e
  Akira Hatanaka authored Dec 19, 2011
```
llvm-svn: 146896
```
  9e1d369e
- Remove definitions of double word shift plus 32 instructions. Assembler or · 2a232d81
  Akira Hatanaka authored Dec 19, 2011
```
direct-object emitter should emit the appropriate shift instruction depending
on the shift amount.

llvm-svn: 146893
```
  2a232d81
- Remove unused predicate. · c4db30e3
  Akira Hatanaka authored Dec 19, 2011
```
llvm-svn: 146889
```
  c4db30e3