this speeds up the bcreader from 6.67s to 0.12s on a testcase Daniel 
provided.  rdar://6158117

llvm-svn: 55090

llvm-svn: 55089

llvm-svn: 55087

llvm-svn: 55085

instead of requiring an std::vector.

llvm-svn: 55084

out of X86ISelDAGToDAG.cpp C++ code and into tablegen code.
Among other things, using tablegen for these things makes them
friendlier to FastISel.

Tablegen can handle the case of i8 subregs on x86-32, but currently
the C++ code for that case uses MVT::Flag in a tricky way, and it
happens to schedule better in some cases. So for now, leave the
C++ code in place to handle the i8 case on x86-32.

llvm-svn: 55078

llvm-svn: 55077

class hold a MachineRegisterInfo member, and make the
MachineBasicBlock be passed in to SelectInstructions rather
than the FastISel constructor.

llvm-svn: 55076

llvm-svn: 55075

llvm-svn: 55074

llvm-svn: 55072

llvm-svn: 55071

llvm-svn: 55070

llvm-svn: 55069

llvm-svn: 55067

and the slow-path cases out of line.  This speeds up instcombine
a bit in real world cases.  Patch contributed by m-s.

llvm-svn: 55063

llvm-svn: 55059

alignment and volatility information, such as loads and
stores, to reduce the number of integer values added to
the FoldingSetNodeID.

llvm-svn: 55058

llvm-svn: 55057

necessary to use dyn_cast in these predicates.

llvm-svn: 55055

llvm-svn: 55054

llvm-svn: 55053

llvm-svn: 55052

llvm-svn: 55050

llvm-svn: 55049

llvm-svn: 55047

llvm-svn: 55035

not have a fall-through successor.

llvm-svn: 55033

llvm-svn: 55031

llvm-svn: 55029

a command-line option, so that the default behavior is an abort, which
is useful for exposing code that isn't supported yet.

llvm-svn: 55028

that aren't available as virtual registers (for now).

llvm-svn: 55026

Just expand it like the other X-bit sub_and_fetches.

llvm-svn: 55023

llvm-svn: 55022

llvm-svn: 55021

llvm-svn: 55020

was already present, but not hooked up to anything.

llvm-svn: 55018

llvm-svn: 55015

llvm-svn: 55014

llvm-svn: 55012