llvm-svn: 83677

lists.  Changed ARMAsmParser::MatchRegisterName to return -1 instead of 0 on
errors so 0-15 values could be returned as register numbers.  Also added the
rest of the arm register names to the currently hacked up version to allow more
testing.  Some changes to ARMAsmParser::ParseOperand to give different errors
for things not yet supported and some additions to the hacked
ARMAsmParser::MatchInstruction to allow more testing for now.

llvm-svn: 83673

when one of the bits being tested would end up being the sign bit in the
narrower type, and a signed comparison is being performed, since this would
change the result of the signed comparison. This fixes PR5132.

llvm-svn: 83670

information when unfolding memory references.

llvm-svn: 83656

llvm-svn: 83600

llvm-svn: 83598

llvm-svn: 83596

Also fix some copy-and-paste errors in previous changes.

llvm-svn: 83590

llvm-svn: 83585

llvm-svn: 83572

llvm-svn: 83568

llvm-svn: 83566

llvm-svn: 83565

llvm-svn: 83556

llvm-svn: 83549

llvm-svn: 83526

llvm-svn: 83522

llvm-svn: 83521

llvm-svn: 83518

llvm-svn: 83513

llvm-svn: 83508

llvm-svn: 83506

llvm-svn: 83502

llvm-svn: 83501

llvm-svn: 83499

llvm-svn: 83494

llvm-svn: 83490

llvm-svn: 83486

llvm-svn: 83484

llvm-svn: 83482

llvm-svn: 83479

with writeback, things like "sp!", etc.  Also added some more stuff to the
temporarily hacked methods ARMAsmParser::MatchRegisterName and
ARMAsmParser::MatchInstruction to allow more parser testing.

llvm-svn: 83477

implementations with a new MachineInstr::isInvariantLoad, which uses
MachineMemOperands and is target-independent. This brings MachineLICM
and other functionality to targets which previously lacked an
isInvariantLoad implementation.

llvm-svn: 83475

llvm-svn: 83471

This is just to be more consistent with the forthcoming code for vld3/4.

llvm-svn: 83470

a virtual register to eliminate a frame index, it can return that register
and the constant stored there to PEI to track. When scavenging to allocate
for those registers, PEI then tracks the last-used register and value, and
if it is still available and matches the value for the next index, reuses
the existing value rather and removes the re-materialization instructions.
Fancier tracking and adjustment of scavenger allocations to keep more
values live for longer is possible, but not yet implemented and would likely
be better done via a different, less special-purpose, approach to the
problem.

eliminateFrameIndex() is modified so the target implementations can return
the registers they wish to be tracked for reuse.

ARM Thumb1 implements and utilizes the new mechanism. All other targets are
simply modified to adjust for the changed eliminateFrameIndex() prototype.

llvm-svn: 83467

and register spills.

llvm-svn: 83435

operands.  Some parsing of arm memory operands for preindexing and postindexing
forms including with register controled shifts.  This is a work in progress.

llvm-svn: 83424

llvm-svn: 83422

llvm-svn: 83421